Infineon PSoC 61 Manuals
Manuals and User Guides for Infineon PSoC 61. We have 1 Infineon PSoC 61 manual available for free PDF download: Reference Manual
Infineon PSoC 61 Reference Manual (647 pages)
Brand: Infineon
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Category: Single board computers
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Size: 6.25 MB
Table of Contents
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Overview19
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Introduction20
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Features20
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Architecture22
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Features34
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Architecture35
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Registers37
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Features42
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Architecture42
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Wait States44
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Features45
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Architecture46
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IPC Channel46
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Features53
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Architecture53
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Fault Report54
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Monitoring56
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Interrupts61
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Features61
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Architecture62
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Architecture81
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Mpu90
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Smpu90
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Ppu91
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Features102
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Architecture103
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Channels103
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Descriptors106
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Transfer Size110
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DMA Controller111
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Pending Triggers112
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Output Triggers112
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Status Registers112
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DMA Performance113
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Features115
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Architecture116
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Channels116
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Descriptors118
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Transfer Size123
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DMAC Controller124
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Channel Logic124
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Output Triggers124
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Features125
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Architecture125
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Instructions126
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Hash Algorithms133
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SHA1 and SHA2133
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Sha3135
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DES and TDES136
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Aes139
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Crc141
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Prng143
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Trng144
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Vector Unit150
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VU Register File152
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Stack153
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Memory Operands154
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Datapath154
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Status Register155
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Instructions156
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Instruction Set157
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Features175
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Architecture175
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DAP Security177
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DAP Power Domain177
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ROM Tables178
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Trace178
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ACK Details180
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JTAG Interface181
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Registers185
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Flash Memory186
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Features186
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Configuration186
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Block Diagram186
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Flash Geometry187
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Flash Controller188
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Wait State Count188
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Power Modes188
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CPU Caches189
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Features190
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Architecture190
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SRAM Usage191
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SROM API Library192
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System Calls193
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Infineon ID193
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Blow Efuse Bit197
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Read Efuse Byte198
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Write Row199
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Program Row201
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Erase All203
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Checksum205
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Compute Hash207
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Directexecute209
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Erase Sector209
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Soft Reset211
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Erase Row212
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Erase Subsector213
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Generatehash214
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Readuniqueid215
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Checkfactoryhash216
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Transitiontorma217
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Boot Code221
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Features221
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ROM Boot221
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Flash Boot232
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Overview232
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Using Flash Boot232
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Header233
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Code Segment233
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Wait Window (14)237
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Set up SP (17)238
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Idle Loop (18)238
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Efuse Memory240
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Features240
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Architecture240
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Device Security242
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Features242
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Architecture242
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Flash Security246
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Features248
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Architecture249
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Power Supply250
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Core Regulators250
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Backup Domain252
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Register List255
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Features256
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Architecture256
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CPU Power Modes259
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CPU Active Mode259
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CPU Sleep Mode259
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Backup Domain261
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Reset State261
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Off State261
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Summary268
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Register List269
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Backup System270
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Features270
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Architecture271
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Power Supply271
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Clocking272
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Calibration273
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Reset273
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Real-Time Clock273
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Alarm Feature275
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PMIC Control276
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Backup Registers277
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Register List277
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Clocking System278
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Features278
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Architecture279
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Clock Sources279
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ECO Trimming280
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Clock Generation281
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Clock Trees287
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Path Clocks287
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Timer Clock289
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Clk_Fast290
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Clk_Peri290
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Clk_Slow290
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Reset System295
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Features295
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Architecture295
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Power-On Reset297
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Brownout Reset297
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External Reset297
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Register List299
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O System300
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Features300
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Architecture301
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Drive Modes303
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GPIO-OVT Pins306
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Interrupt310
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Analog I/O313
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LCD Drive313
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Capsense313
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Smart I/O314
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Overview314
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Block Components314
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Clock and Reset315
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Synchronizer316
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Data Unit (DU)320
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Routing324
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Operation324
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Registers326
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Watchdog Timer327
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Features327
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Architecture327
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Free-Running WDT328
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Overview328
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Watchdog Reset330
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Overview332
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MCDWT Reset339
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MCWDT Interrupt339
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Register List340
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Features341
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Architecture341
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Register List345
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Features348
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Block Diagram349
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Clocking350
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Clock Gating350
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Bus Speed Modes351
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Power Modes352
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Standby Mode352
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SDIO Interrupt353
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I/O Interface353
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DMA Engine355
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Enabling SDHC357
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Card Detection357
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Clock Setup360
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Error Detection361
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Features362
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Architecture363
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Buffer Modes363
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FIFO Mode363
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EZ Mode363
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CMD_RESP Mode363
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Clocking Modes364
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Features365
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Motorola SPI367
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SPI Buffer Modes372
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FIFO Mode372
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EZSPI Mode373
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Clock Modes378
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SPI Master382
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SPI Slave383
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Median Filter384
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SPI Registers384
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Uart385
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Features385
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Smartcard Mode398
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LIN Mode399
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Irda Mode400
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UART Registers400
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Features401
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Clock Stretching403
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Bus Arbitration404
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Write Transfer405
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Read Transfer405
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I2C Buffer Modes406
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FIFO Mode406
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EZI2C Mode407
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Glitch Filtering411
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I2C Registers416
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SCB Interrupts417
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SPI Interrupts418
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UART Interrupts421
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I2C Interrupts425
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Features427
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Architecture427
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Tx and Rx Fifos429
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Tx Command FIFO429
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Tx Data FIFO430
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Rx Data FIFO430
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Command Mode431
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XIP Mode431
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Cache432
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Arbitration432
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Deselect Delay432
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Cryptography433
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Triggers443
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Interrupts444
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Sleep Operation444
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Performance444
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Overview445
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Features445
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Configuration446
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Block Diagram446
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Interrupt Lines446
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Operation Modes447
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Normal Operation448
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CAN FD Operation448
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Test Mode452
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Timeout Counter454
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RX Handling454
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RX Fifos458
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TX Handling462
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Transmit Pause463
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Tx Fifo464
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TX Queue464
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CAN Bit Timing467
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CAN Bit Rates469
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Message RAM470
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Mram off484
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TTCAN Operation484
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Level 1485
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Level 2485
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Level 0485
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TTCAN Timing486
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Trigger Memory488
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Stop Watch494
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Level 0501
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Synchronizing502
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Setup Procedures504
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Registers518
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Features522
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Architecture523
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Clocking524
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Clock Prescaling524
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Count Input524
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Trigger Inputs524
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Trigger Outputs526
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Interrupts527
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PWM Outputs527
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Power Modes528
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Operation Modes528
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Timer Mode529
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Capture Mode536
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Asymmetric PWM552
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TCPWM Registers560
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Features562
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Architecture562
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USB Bus Reset565
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USB Packets566
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Token Packet566
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Data Packet571
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Handshake Packet571
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Retry Function571
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Error Status572
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Resume Operation578
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Features581
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Architecture582
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Arbiter583
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Memory Interface583
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Arbiter Logic583
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Operation583
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Usb Phy584
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Power Scheme584
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VBUS Detection584
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GPIO Mode Logic585
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Endpoints585
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Transfer Types586
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RESUME Interrupt587
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DMA Support589
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USB Power Modes601
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LCD Direct Drive603
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Features603
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Architecture603
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Drive Modes604
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PWM Drive604
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Register List616
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Analog Subsystem617
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Features618
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Architecture618
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Startup Modes619
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Registers620
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Features621
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Architecture622
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Hysteresis625
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Comparator Clock625
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Register List626
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Sar Adc627
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Features627
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Architecture628
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SAR ADC Core628
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Input Range629
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Acquisition Time632
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SAR ADC Clock632
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SAR ADC Timing633
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Sarmux633
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Analog Routing634
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Sarref635
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Sarseq636
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Averaging637
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Range Detection638
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Double Buffer638
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SAR Interrupts638
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Trigger640
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SAR ADC Status640
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Registers641
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Features642
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Architecture642
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Algorithm644
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Registers644
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Capsense645
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Revision History646
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