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PRELIMINARY
CYW43353
Statistics counters for MIB support
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10.1.1 PSM
The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to
implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are pre-
dominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general,
which allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track
evolving IEEE 802.11 specifications.
The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data
store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad
memory (similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers (IHR). These IHRs
are co-located with the hardware functions they control, and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal,
or a program stack. For ALU operations the operands are obtained from shared memory, scratch-pad, IHRs, or instruction literals,
and the results are written into the shared memory, scratch-pad, or IHRs.
There are two basic branch instructions: conditional branches and ALU based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condi-
tion signals are available to the PSM without polling the IHRs), or on the results of ALU operations.
10.1.2 WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption,
and MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2
AES-CCMP.
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to be used. It supplies
the keys to the hardware engines from an on-chip key table. The WEP interfaces with the TXE to encrypt and compute the MIC on
transmit frames, and the RXE to decrypt and verify the MIC on receive frames.
10.1.3 TXE
The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit
frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at
the appropriate time determined by the channel access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic
streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to sched-
ule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on
a precise timing trigger received from the IFS module.
The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hard-
ware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
10.1.4 RXE
The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received
frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames.
The decrypted data is stored in the RXFIFO.
The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria
such as receiver address, BSSID, and certain frame types.
The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.
Document Number: 002-14949 Rev. *G
Page 51 of 113
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