Table of Contents
Advertisement
VBAT*
VDDIO
WL_REG_ON
VDDC
(from internal PMU)
Internal POR
Device requests for reference clock
Host Interaction:
Host polls F0 (address 0x14) until it reads a
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 25. WLAN Boot-Up Sequence
< 950 µs
< 104 ms
< 4 ms
predefined pattern.
After a fixed delay following Internal POR and WL_REG_ON going high,
the device responds to host F0 (address 0x14) reads.
8 ms
Host sets wake‐up‐wlan bit and
waits 8 ms, the maximum time for
reference clock availability.
Chip active interrupt is asserted after the PLL locks
CYW43353
After 8 ms the reference clock is
assumed to be up. Access to PLL
registers is possible.
After 8 ms, host programs PLL
registers to set crystal frequency
Host downloads
code.
Page 49 of 113
Advertisement
Table of Contents
