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16.4 CLDO
Table 40. CLDO Specifications
Specification
Input supply voltage, V
in
Output current
Output voltage, V
o
Dropout voltage
Output voltage DC accuracy
Quiescent current
Line regulation
Load regulation
Leakage current
PSRR
Start-up time of PMU
LDO turn-on time
External output capacitor, C
External input capacitor
1.
Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-14949 Rev. *G
PRELIMINARY
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement
must be met under maximum load.
–
Programmable in 25 mV steps. Default = 1.2.V
At max. load
Includes line/load regulation
No load
300 mA load
V
from (V
+ 0.15V) to 1.5V, maximum load
in
o
Load from 1 mA to 300 mA
Power down
Bypass mode
@1 kHz, Vin ≥ 1.35V, C
VIO up and steady. Time from the REG_ON rising edge to
the CLDO reaching 1.2V.
LDO turn-on time when rest of the chip is up
Total ESR: 5 mΩ–240 mΩ
o
Only use an external input capacitor at the VDD_LDO pin if
it is not supplied from CBUCK output.
Notes
= 4.7 µF
o
CYW43353
Min.
Typ.
Max.
1.3
1.35
1.5
0.2
–
300
1.1
1.2
1.275
–
–
150
–4
–
+4
–
24
–
–
2.1
–
–
–
5
–
0.02
0.05
–
–
20
–
1
3
20
–
–
–
700
–
140
180
4.7
–
1
1.32
–
1
2.2
Page 90 of 113
Units
V
mA
V
mV
%
µA
mA
mV/V
mV/mA
µA
µA
dB
µs
µs
µF
µF
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