Infineon PSoC 61 Reference Manual

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PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5

architecture

Reference manual

About this document

Scope and purpose

This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of

the PSoC™ 6 MCU device hardware.

Intended audience

This document is intended for anyone who use the PSoC™ 6 MCU device.

Reference manual

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

002-27293 Rev. *E

2023-09-06

Table of Contents

Summary of Contents for Infineon PSoC 61

Page 1: About This Document
PSoC™ 6 MCU device hardware. Intended audience This document is intended for anyone who use the PSoC™ 6 MCU device. Reference manual Please read the Important Notice and Warnings at the end of this document 002-27293 Rev. *E www.infineon.com page 1 2023-09-06...
Page 2: Table Of Contents
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents Table of contents About this document Scope and purpose Intended audience Table of contents Section A: Overview Introduction ..............20 Features .
Page 3 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents Fault monitoring ..............53 Features .
Page 4 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 9.7.4 PPU ..................91 9.7.5 Protection of protection structures .
Page 5 Infineon ID ........
Page 6 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 14.5.3 Read eFuse byte ................198 14.5.4 Write row .
Page 7 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 15.3.5.11 Enable system calls (10) ..............237 15.3.5.12 Is DAP enabled (11) .
Page 8 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 19.2.1.3 CPU Deep Sleep mode ..............259 19.2.2 System power modes .
Page 9 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 21.5.3 Medium-frequency clock ..............289 21.5.4 Low-frequency clock .
Page 10 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 23.9.1 Overview ................. 314 23.9.2 Block components .
Page 11 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 26.6.1 SDIO interrupt ................353 26.7 I/O interface .
Page 12 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 27.4.3.3 SmartCard (ISO 7816) ..............395 27.4.3.4 Infrared Data Association (IrDA) .
Page 13 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 28.3 Memory device signal interface ............. 434 28.3.1 Specifying memory devices .
Page 14 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 29.4 Message RAM ................470 29.4.1 Message RAM configuration .
Page 15 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 30.2.1 Enabling and disabling counters in a TCPWM block ......... . . 523 30.2.2 Clocking .
Page 16 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 31.3.10.2 Resume operation ..............578 31.3.11 Device disconnection .
Page 17 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 33.3 PSoC™ 6 MCU segment LCD direct drive ........... . . 614 33.3.1 High-speed and low-speed master generators .
Page 18 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Table of contents 36.2.5.1 End-of-scan interrupt (EOS_INTR) ............639 36.2.5.2 Overflow interrupt .
Page 19: Overview
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Overview Section A: Overview This section encompasses the following chapters: • “Introduction” on page 20 • “Getting started” on page 24 • “Document organization and conventions” on page 25 Reference manual 002-27293 Rev. *E 2023-09-06...
Page 20: Introduction
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Introduction Introduction This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 21 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Introduction Quad-SPI (QSPI)/serial memory interface (SMIF) • Execute-In-Place (XIP) from external Quad SPI flash • On-the-fly encryption and decryption • 4-KB cache for greater XIP performance with lower power • Supports single, dual, quad, dual-quad, and octal interfaces Segment LCD drive •...
Page 22: Psoc™ 61 And Psoc™ 62 Mcu Series Differences
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Introduction PSoC™ 61 and PSoC™ 62 MCU series differences There is only one difference between the PSoC™ 61 (CY8C61x5) and the PSoC™ 62 (CY8C62x5) series MCUs. • In the PSoC™ 62 series, both the CPUs (Cortex®-M4F and Cortex® M0+) are available for applications. •...
Page 23 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Introduction The block diagram shows the device subsystems and gives a simplified view of their interconnections. The color- code shows the lowest power mode where the particular block is still functional (for example, LP comparator is functional in Deep Sleep and Hibernate modes).
Page 24: Getting Started
PSoC™ 6 MCU resources This chapter provides the complete list of PSoC™ 6 MCU resources that helps you get started with the device and design your applications with them. If you are new to PSoC™, Infineon provides a wealth of data at www.infineon.com to help you to select the right PSoC™...
Page 25: Document Organization And Conventions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Document organization and conventions This document includes the following sections: • “CPU subsystem” on page 33 • “System resources subsystem (SRSS)” on page 247 • “Digital subsystem” on page 347 •...
Page 26: Acronyms And Initializations
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-1. Units of measure (continued) Abbreviation Unit of measure Giga Hertz kilo, 1000 kilo, 2^10 1024 bytes, or approximately one thousand bytes Kbit 1024 bits kilohertz (32.000) k kilohms megahertz M...
Page 27 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer bus application programming interface APOR analog power-on reset broadcast clock binary coded decimal BESL best effort service latency...
Page 28 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition DMIPS Dhrystone million instructions per second differential nonlinearity digital or data output digital signal processing Deep Sleep mode data unit data wire external crystal oscillator EEPROM electrically erasable programmable read only memory...
Page 29 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition identity resolution key interrupt request instruction set architecture interrupt service routine instrumentation trace macrocell interrupt vector read IZTAT zero dependency to absolute temperature JSON web token L2CAP logical link control and adaptation protocol...
Page 30 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition over-sampling ratio over-voltage protection power amplifier program counter printed circuit board program counter high program counter low power down protocol data unit programmable gain amplifier physical layer programmable logic device...
Page 31 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition single-ended zero switched capacitor serial communication block SHA-256 Secure Hash Algorithm serial interface engine SIMO single input multiple output special I/O signal-to-noise ratio SMPU shared memory protection units...
Page 32 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition VTOR vector table offset register watch crystal oscillator watchdog timer watchdog reset wakeup interrupt controller XRES external reset XRES_N external reset, active low Reference manual 002-27293 Rev.
Page 33: Cpu Subsystem
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem Section B: CPU subsystem This section encompasses the following chapters: • “CPU subsystem (CPUSS)” on page 34 • “SRAM controller” on page 42 • “Inter-processor communication” on page 45 • “Fault monitoring” on page 53 •...
Page 34: Cpu Subsystem (Cpuss)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) CPU subsystem (CPUSS) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 35: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) Architecture CPU Subsystem Cortex® M4F CPU 150/50 MHz, 1.1/0.9 V SWJ, ETM, ITM, CTI Cortex® M0+ CPU 100/25 MHz, 1.1/0.9 V SWJ, MTB, CTI 3x DMA Controller Crypto DES/TDES, AES, SHA, CRC, TRNG, RSA/ECC Accelerator Color Key:...
Page 36: Address And Memory Maps
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) 4.2.1 Address and memory maps Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided into the regions shown in Table 4-1.
Page 37: Wait State Lookup Tables
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) 4.2.1.1 Wait state lookup tables The wait state lookup tables show the wait states for Flash, SRAM, and ROM based on the Clk_HF0 frequency and the current power mode. SRAM and ROM have two domains for the wait states – fast clock domain (Clk_Fast) and slow clock domain (Clk_Slow);...
Page 38 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) Table 4-3. Cortex®-M4 and Cortex®-M0+ Registers (continued) Name Type Reset value Description Undefined The program status register (PSR) combines: Application Program Status Register (APSR). Execution Program Status Register (EPSR). Interrupt Program Status Register (IPSR). APSR Undefined The APSR contains the current state of the condition flags from previous...
Page 39 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) Table 4-4. Cortex®-M4 PSR bit assignments (continued) Name Usage Register APSR Carry or borrow flag APSR Overflow flag APSR DSP overflow and saturation flag 26 – 25 EPSR IC/IT Control interrupt-continuable and IT instructions EPSR Thumb state bit.
Page 40: Operating Modes And Privilege Levels
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) Table 4-5. Cortex®-M0+ PSR bit assignments (continued) Name Usage Register 23 – 6 – – Reserved 5 – 0 IPSR Excepti Exception number of current ISR: 0 = thread mode Number 1 = reserved 2 = NMI...
Page 41: Instruction Set
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CPU subsystem (CPUSS) Instruction set Both CPUs implement subsets of the Thumb instruction set, as Table 4-6 shows. The table does not show the large number of variants and conditions of the instructions. For details, see one of the Arm® Cortex® generic user guides or technical reference manuals.
Page 42: Sram Controller
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SRAM controller SRAM controller This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 43 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SRAM controller Partial AHB-Lite write transfers A partial AHB-Lite write transfer is translated into an SRAM read access and an SRAM write access. The SRAM read access is the direct result of the partial write transfer and the SRAM write access is the result of a write buffer request.
Page 44: Wait States
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SRAM controller Wait states The programmable wait states represent the number of clk_hf cycles for a read path through the SRAM memory to flipflops in either the fast domain (CM4 CPU) or slow domain (such as CM0+ CPU, DataWire, and DMA controller).
Page 45: Inter-Processor Communication
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication Inter-processor communication This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 46: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication Architecture 6.2.1 IPC channel An IPC channel is implemented as six hardware registers, as shown in Figure 6-2. The IPC channel registers are accessible to all the processors in the system. •...
Page 47: Ipc Interrupt
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication 6.2.2 IPC interrupt Each IPC interrupt line in the system has a corresponding IPC interrupt structure. An IPC interrupt can be triggered by a notify or a release event from any of the IPC channels in the system. You can choose to mask any of the sources of these events using the IPC interrupt registers.
Page 48: Implementing Locks
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication IPC 0 IPC 1 IPC N Release Notify Release Notify Release Notify INTR N INTR N INTR N INTR N INTR N INTR N INTR 3 INTR 3 INTR 3 INTR 3 INTR 3 INTR 3 INTR 2...
Page 49: Message Passing
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication Message passing IPC channels can be used to communicate messages between processors. In this use case, the channel is used in conjunction with the interrupt structures. The IPC channel is used to lock the access to the data registers. The IPC channel is acquired by the sender and used to populate the message.
Page 50: Typical Usage Models
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication In the previous example, the size of the data being transmitted was just 64 bits. Larger messages can be sent as pointers. The sender can allocate a larger message structure in memory and pass the pointers in the data registers.
Page 51: Half Duplex With Independent Event Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication IPC Interrupt X System Interrupt IPC Channel X Core 0 Core 1 IPC Channel Y System IPC Interrupt Y Interrupt Data transfer/register updates over system bus Digital signals such as triggers or interrupts Figure 6-7.
Page 52: Half Duplex With Shared Event Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Inter-processor communication 6.5.3 Half duplex with shared event handling In this model both the IPC channel and interrupt are shared between the two cores. Since the interrupt is also shared, the access to the interrupt registers must be managed using the IPC lock of the channel. As shown in Figure 6-9, the IPC interrupt will be set up to trigger interrupts in both cores.
Page 53: Fault Monitoring
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring Fault monitoring This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 54: Fault Report
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring The PSoC™ 6 MCU family uses centralized fault report structures. This centralized nature allows for a system wide handling of faults simplifying firmware development. Only a single fault interrupt handler is required to monitor multiple faults.
Page 55 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring Table 7-1. Fault information Fault source Fault information MPU/SMPU violation DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure.
Page 56: Signaling Interface
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring 7.2.2 Signaling interface In addition to captured fault information, each fault report structure supports a signaling interface to notify the system about the captured fault. The interface of fault report structure ‘x’ supports the following: •...
Page 57: Low-Power Mode Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring • One fault report structure is used to capture recoverable faults and one fault report structure is used to capture non-recoverable faults. The former can be used to generate a fault interrupt and the latter can be used to activate a chip output signal and/or activate a reset request.
Page 58: Cpu Exceptions Versus Fault Monitoring
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring c) Use the signal externally for processing the fault – generate external reset, power cycle, or log fault information. 5. Set the RESET_REQ_EN bit [2] of the FAULT_STRUCTx_CTL register, if a soft reset is required on any fault detection in the structure.
Page 59: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring Table 7-2. Fault sources (continued) Fault index Source Description peri.group_vio[2] Peripheral group #2 (CPUSS, SRSS, EFUSE) PPU violation Register address range: 0x40200000 to 0x40300000 peri.group_vio[3] Peripheral group #3 (IOSS, LPCOMP, CSD, TCPWM, LCD, BLE) PPU violation Register address range: 0x40300000 to 0x40400000 peri.group_vio[4]...
Page 60 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Fault monitoring Table 7-3. Register list (continued) Name Description FAULT_STRUCTx_MASK0 Fault mask register 0 that enables the capture of pending faults with fault index from 0 to 31 by the fault structure FAULT_STRUCTx_MASK1 Fault mask register 1 that enables the capture of pending faults with fault index from 32 to 63 by the fault structure FAULT_STRUCTx_MASK2...
Page 61: Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Interrupts This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 62: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Architecture PSoC™ 6 MCU Interrupt Architecture M0+ interrupt settings Enable / Disable Interrupt Set Priority CPUSS_CM0_SYSTEM_INT_CTLx Mask Interrupt Set NMI source Each IRQn can be Software trigger connected to one or more of the 174 interrupt sources M0+ processor INT Source 0...
Page 63: Interrupts And Exceptions - Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts as soon as one CPU wakes up. The synchronization blocks synchronize the interrupts to the CPU clock frequency as the peripheral interrupts can be asynchronous to the CPU clock frequency. Interrupts and exceptions - operation 8.3.1 Interrupt/exception handling The following sequence of events occurs when an interrupt or exception event is triggered:...
Page 64: Level And Pulse Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts 8.3.2 Level and pulse interrupts Both CM0+ and CM4 NVICs support level and pulse signals on the interrupt lines (IRQn). The classification of an interrupt as level or pulse is based on the interrupt source. IRQn IRQn is still high Execution...
Page 65 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Table 8-1. M0+ exception vector table (continued) Exception Exception Exception priority Vector address number 12-13 Reserved Start_Address + 0x30 to Start_Address + 0x34 PendSupervisory (PendSV) Configurable (0 – 3) Start_Address + 0x38 System Timer (SysTick) Configurable (0 –...
Page 66: Exception Sources
Cortex®-M0+ out of supervisory read-only memory (SROM). The boot code and other data in SROM memory are programmed by Infineon, and are not read/write accessible to external users. After completing the SROM boot sequence, the Cortex®-M0+ code execution jumps to flash memory.
Page 67: Hardfault Exception
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts CPUSS_CM4_NMI_CTLx CPUSS_CM0P_NMI_CTLx INT Source 0 1023 System interrupt INT Source 1 sources CM4 NMI 1023 INT Source 2 n <= 1023 CM0+ NMI (device dependent) 1023 INT Source n-1 1023 Figure 8-5. NMI trigger •...
Page 68: Bus Fault Exception
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts 8.4.5 Bus Fault exception A Bus Fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. The bus fault is supported only by the M4 core.
Page 69: System Tick (Systick) Exception
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts 8.4.9 System Tick (SysTick) exception Both CM0+ and CM4 cores in PSoC™ 6 MCUs support a system timer, referred to as SysTick, as part of their internal architecture. SysTick provides a simple, 24-bit decrementing counter for various timekeeping purposes such as an RTOS tick timer, high-speed alarm timer, or simple counter.
Page 70 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts system_int_idx = CPUSS_CM0_INT0_STATUS.SYSTEM_INT_IDX; handler = SystemIntr_Table[system_int_idx]; handler(); // jump to system interrupt handler else // Triggered by SW or due to SW clear error (SW cleared a peripheral // interrupt flag but didn't clear the Pending flag at NVIC) …...
Page 71 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Sleep wakeup-capable interrupts can be connected to any of the eight IRQ lines of Cortex®-M0+, if such a wakeup is desired. Table 8-3. List of PSoC™ 6 interrupt sources System Cortex® M4 Power mode Interrupt source interrupt...
Page 72 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Table 8-3. List of PSoC™ 6 interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ33 DeepSleep CPUSS Inter Process Communication Interrupt #10 IRQ34 DeepSleep CPUSS Inter Process Communication Interrupt #11 IRQ35 DeepSleep CPUSS Inter Process Communication Interrupt #12...
Page 73 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Table 8-3. List of PSoC™ 6 interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ70 Active CPUSS DataWire #0, Channel #14 IRQ71 Active CPUSS DataWire #0, Channel #15 IRQ72 Active CPUSS DataWire #0, Channel #16...
Page 74 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Table 8-3. List of PSoC™ 6 interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ107 Active CPUSS DataWire #1, Channel #22 IRQ108 Active CPUSS DataWire #1, Channel #23 IRQ109 Active CPUSS DataWire #1, Channel #24...
Page 75 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Table 8-3. List of PSoC™ 6 interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ144 Active Not available IRQ145 Active Not available IRQ146 Active Not available IRQ147 Active Not available IRQ148...
Page 76: Interrupt/Exception Priority
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts Interrupt/exception priority Exception priority is useful for exception arbitration when there are multiple exceptions that need to be serviced by the CPU. Both M4 and M0+ cores in PSoC™ 6 MCUs provide flexibility in choosing priority values for different exceptions.
Page 77: Interrupt/Exception States
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts For CM0+, the first 16 bits of the ISER and ICER registers are valid. See the “Interrupt sources” on page 69 for details on how to map a CPU interrupt to a system interrupt in CM0+. Figure 8-6.
Page 78: Pending Interrupts/Exceptions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts • The ISRPENDING bit (bit 22) in the ICSR indicates if a NVIC generated interrupt is in a pending state. 8.8.1 Pending interrupts/exceptions When a peripheral generates an interrupt request signal to the NVIC or an exception event occurs, the corresponding exception enters the pending state.
Page 79: Interrupts And Low-Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts 8.10 Interrupts and low-power modes The PSoC™ 6 MCU family allows device (CPU) wakeup from low-power modes when certain peripheral interrupt requests are generated. The Wakeup Interrupt Controller (WIC) block generates a wakeup signal that causes the CPU to enter Active mode when one or more wakeup sources generate an interrupt signal.
Page 80: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Interrupts c) For Cortex®-M0+, define and enable the additional system interrupt handler table and functions as explained in “Interrupt sources” on page 69. d) Set up the exception priority, as explained in “Interrupt/exception priority” on page 76.
Page 81: Protection Units
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Protection units This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 82: Psoc™ 6 Protection Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units • Protection structure: A protection structure is a register structure in memory that sets up the rules based on which each protection unit will evaluate a transfer. Each protection unit associates itself to multiple protection structures.
Page 83 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units – An MPU that is implemented as part of the bus infrastructure. This type is found in bus masters such as crypto and test controller. The definition of this MPU type follows the Arm® MPU definition (in terms of memory region and access attribute definition) to ensure a consistent software interface.
Page 84 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units A protection violation results in a bus error and the bus transfer will not reach its target. An MPU or SMPU violation that targets a peripheral will not reach the associated protection evaluation (PPU). In other words, MPU and SMPU have a higher priority over PPU.
Page 85: Register Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Register architecture The protection architecture has different conceptual pieces and different sets of registers correspond to each of these concepts. 9.3.1 Protection structure and attributes The MPU, SMPU, and PPU protection structure definition follows the Arm® definition. Each protection structure is defined by: •...
Page 86 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units The execute and read access control attributes are orthogonal. Execute transfers are typically read transfers. To allow execute and read transfers in user mode, both ATT.UR and ATT.UX must be set to ‘1’. To allow data and read transfers in user mode, only ATT.UR must be set to ‘1’.
Page 87: Bus Master Protection Attributes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Note: • If no protection structure provides a match, the access is allowed. • If multiple protection structures provide a match, the access control attributes for the access evaluation are provided by the protection structure with the highest index. An example of using the PC_MATCH feature is as follows.
Page 88: Protection Context
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Protection context Each bus master has a MPU MS_CTL.PC[3:0] protection context field. This protection context is used as the protection context attribute for all bus transfers that are initiated by the master. The SMPUs and PPUs allow or restrict bus transfers based on the protection context attribute.
Page 89: Protection Structure
It has unrestricted access; that is, it is not affected by the CPUSS and PERI protection schemes. Therefore, the Infineon boot code software always starts execution in PC 0. The boot code software initializes the protection structures and initializes the CM0_PCi_HANDLER registers. The boot code is considered “trusted” software and its unrestricted access in PC 0 is not considered a protection concern.
Page 90: Mpu
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units 9.7.2 The MPUs are situated in the CPUSS and are associated to a single master. An MPU distinguishes user and privileged accesses from a single bus master. However, the capability exists to perform access control on the secure/non-secure attribute.
Page 91: Ppu
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units 9.7.4 • The PPUs are situated in the PERI block and are associated with a peripheral group (a group of peripherals with a shared AHB-Lite bus infrastructure). A PPU is shared by all bus masters. The PPU distinguishes between different protection contexts;...
Page 92 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX8 0x40004120 32 B Peripheral Group Structure 9 PERI_MS_PPU_FX9 0x40008000 32 KB Peripheral Trigger Group PERI_MS_PPU_FX10 0x40100000...
Page 93 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX45 0x402210C0 16 B IPC Interrupt Structure 6 PERI_MS_PPU_FX46 0x402210E0 16 B IPC Interrupt Structure 7 PERI_MS_PPU_FX47 0x40221100...
Page 94 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX82 0x40290000 128 B DMA Controller (DW) 1 PERI_MS_PPU_FX83 0x40280100 128 B DMA Controller (DW) 0 CRC PERI_MS_PPU_FX84 0x40290100...
Page 95 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX104 0x402884C0 64 B DMA Controller (DW) 0 Channel Structure 19 PERI_MS_PPU_FX105 0x40288500 64 B DMA Controller (DW) 0 Channel...
Page 96 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX124 0x40298280 64 B DMA Controller (DW) 1 Channel Structure 10 PERI_MS_PPU_FX125 0x402982C0 64 B DMA Controller (DW) 1 Channel...
Page 97 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX144 0x40298780 64 B DMA Controller (DW) 1 Channel Structure 30 PERI_MS_PPU_FX145 0x402987C0 64 B DMA Controller (DW) 1 Channel...
Page 98 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX179 0x40310580 64 B GPIO Port 11 PERI_MS_PPU_FX180 0x40310600 64 B GPIO Port 12 PERI_MS_PPU_FX181 0x40310680 64 B...
Page 99 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units Table 9-2. Fixed PPU structures (continued) Protection structure Base address of Size of protected Protected block protected region region PERI_MS_PPU_FX216 0x40630000 64 KB SCB 3 PERI_MS_PPU_FX217 0x40640000 64 KB SCB 4 PERI_MS_PPU_FX218 0x40650000 64 KB...
Page 100: Protection Of Protection Structures
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units 9.7.5 Protection of protection structures The MPU, SMPU, and PPU-based protection architecture is consistent and provides the flexibility to implement different system-wide protection schemes. Protection structures can be set once at boot time or can be changed dynamically during device execution.
Page 101 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Protection units As mentioned earlier, a protection unit evaluates the protection regions in decreasing protection structure index order. The protection structures are evaluated in the following order: • Fixed protection structures for specific peripherals or peripheral register address ranges. •...
Page 102: Dma Controller (Dw)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) DMA controller (DW) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 103: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) 10.2 Architecture Pending Priority Data Transfer Engine Trigger out System triggers Decoder (active request) Triggers Interrupt Bus slave Bus master Trigger interface registers interface Multiplexer Descriptors Descriptors Descriptors Memory Figure 10-1. DMA controller A data transfer is initiated by an input trigger.
Page 104 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) Table 10-1. Channel states Channel state Description Disabled The channel is disabled by setting CHi_CTL.ENABLED to ‘0’. The channel trigger is ignored in this state. Blocked The channel is enabled and is waiting for a trigger to initiate a data transfer. Pending The channel is enabled and has received an active trigger.
Page 105: Channel Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) 10.3.1 Channel interrupts Every DMA channel has an interrupt line associated with it. The INTR_TYPE parameter in the descriptor determines the event that will trigger the interrupt for the channel. In addition each DMA channel has INTR, INTR_SET, INTR_MASK, and INTR_MASKED registers to control their respective interrupt lines.
Page 106: Descriptors
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) 10.4 Descriptors The data transfer between a source and destination in a channel is configured using a descriptor. Descriptors are stored in memory. The descriptor pointer is specified in the DMA channel registers. The DMA controller does not modify the descriptor and treats it as read only.
Page 107 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) Single transfer: The following pseudo code illustrates a single transfer. // DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE // SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE // t_DATA_SIZE is the type associated with the DATA_SIZE DST_ADDR[0] = (t_DATA_SIZE) SRC_ADDR[0];...
Page 108: Address Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) Descriptor DESCR_SRC Source Address DESCR_DST Destination Address DESCR_CTL DESCR_TYPE TR_IN_TYPE TR_OUT_TYPE SCR_TRANSFER_SIZE DST_TRANSFER_SIZE DATA_SIZE INTR_TYPE CH_DISABLE WAIT_FOR_DEACT X Size SRC_X_INR DST_X_INCR Y Size SRC_Y_INR DST_Y_INCR DESCR_NEXT_PTR Next Descriptor Address Figure 10-2. Descriptor structure 10.4.1 Address configuration Source and destination address: The source and destination addresses are set in the respective registers in the...
Page 109 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) • Type 3: Generates a trigger output on completion of the current descriptor, when the current descriptor is the last descriptor in the descriptor chain. This means a trigger is generated when the descriptor execution is complete and the DESCR_NEXT_PTR is ‘0’.
Page 110: Transfer Size
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) Destination address increment (X loop) (DST_X_INCR): This field configures the index by which the destination address is to be incremented, for every iteration in an X loop. The field is expressed in multiples of DST_TRANSFER_SIZE.
Page 111: Descriptor Chaining
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) Table 10-3. Transfer size settings (continued) DATA_SIZE SCR_TRANSFER DST_TRANSFER Typical usage Description _SIZE _SIZE 16-bit 32-bit 16-bit Peripheral to Higher 16 bits from the source Memory dropped 16-bit 16-bit 32-bit Memory to Higher 16 bits zero padded at Peripheral...
Page 112: Pending Triggers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) 10.5.2 Pending triggers Pending triggers keep track of activated triggers by locally storing them in pending bits. This is essential because multiple channel triggers may be activated simultaneously, whereas only one channel can be served by the data transfer engine at a time.
Page 113: Dma Performance
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) 10.5.5 DMA performance The DMA block works on the clk_slow domain and hence all clocks described in this section are in clk_slow units. Every time a DMA channel is triggered the DMA hardware goes through the following steps: •...
Page 114 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMA controller (DW) Note: Descriptors in memory and memory wait states will also affect the descriptor load delay. • Wait states: Memory accesses can have a wait state associated with them. These wait states need to be accounted into the calculation of throughput.
Page 115: Dmac Controller (Dmac)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) DMAC controller (DMAC) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 116: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) 11.2 Architecture A data transfer is initiated by an input trigger. This trigger may originate from the source peripheral of the transfer, the destination peripheral of the transfer, CPU software, or from another peripheral. Triggers provide Active/Sleep functionality and are not available in Deep Sleep and Hibernate power modes.
Page 117: Channel Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) • INTR_MASKED. Logical AND of corresponding INTR and INTR_MASK fields. Note that channel state is retained in Deep Sleep power mode. A channel has three access control attributes that are used by the shared memory protection units (SMPUs) and peripheral protection units (PPUs) for access control.
Page 118: Descriptors
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) 11.4 Descriptors The data transfer between a source and destination in a channel is configured using a descriptor. Descriptors are stored in memory. The descriptor pointer is specified in the DMAC channel registers. The DMAC controller does not modify the descriptor and treats it as read only.
Page 119 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) Table 11-1. Descriptor types (continued) Descriptor type Description Memory copy This is a special case of 1D transfer; DESCR_X_INCR.SRC_X_INCR and DESCR_X_INCR.DST_X_INCR are implicitly set to 1 and not as part of the descriptor (source and destinations data are consecutive).
Page 120: Address Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) Memory copy: The following pseudo code illustrates a memory copy. // DST_ADDR is a pointer to an object of type uint8_t // SRC_ADDR is a pointer to an object of type uint8_t // This transfer type uses 8-bit, 16-bit an 32-bit transfers.
Page 121 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) DESCR_TYPE: This field configures whether the descriptor has a single, 1D, 2D type, memory copy, or scatter transfer. Source data prefetch, DATA_PREFETCH: When enabled, source data transfers are initiated as soon as the channel is enabled;...
Page 122 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) WAIT_FOR_DEACT: When the DMAC transfer based on the TR_IN_TYPE is completed, the data transfer engine checks the state of trigger deactivation. The data transfer on the second trigger is initiated only after deactivation of the first.
Page 123: Transfer Size
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) 11.4.2 Transfer size The word width for a transfer can be configured using the transfer/data size parameter in the descriptor. The settings are diversified into source transfer size, destination transfer size, and data size. The data size parameter (DATA_SIZE) sets the width of the bus for the transfer.
Page 124: Dmac Controller
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture DMAC controller (DMAC) 11.5 DMAC controller DMA c ontroller Channel0 logic Trigger tr_in[0] multiplexers Pending trigger Data transf er engine tr_ out[] Channel state System Triggers Priority decoder tr_in[1] Channel2 logic ……... tr_in[ CH_ NR- 1] Channel31 logic Bus slave Bus master...
Page 125: Cryptographic Function Block (Crypto)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Cryptographic function block (Crypto) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 126: Instruction Controller
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) The crypto block has the following interfaces: • An AHB-Lite slave interface connects the block to the AHB-Lite infrastructure. This interface supports 8/16/32- bit AHB-Lite transfers. MMIO register accesses are 32-bit only. Memory buffer accesses can be 8/16/32-bit. •...
Page 127: Instruction Operands
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) • The INTR.INSTR_OPC_ERROR interrupt cause is activated when an instruction's operation code is not defined. • The INTR.INSTR_CC_ERROR interrupt cause is activated when a vector unit instruction has an undefined condition code.
Page 128: Load And Store Fifo Instructions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.3.3 Load and store FIFO instructions The load and store FIFOs provide access to operand data in a “streaming” nature. Operand data is streamed through the memory interface from or to either the internal memory buffer or the system memory. Two independent load FIFOs provide access to streamed source operand data.
Page 129: Register Buffer Instructions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-3. FF_CONTINUE Instruction Instruction format FF_CONTINUE (ff_identifier, address[31:0], size[31:0]) Encoding IW0[31:24] = “operation code” IW0[3:0] = ff_identifier // “8”: load FIFO 0, // “9”: load FIFO 1, IW1[31:0] = address[31:0] IW2[31:0] = size[31:0]...
Page 130 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-5. SWAP instruction Instruction format SWAP () Encoding IW[31:24] = “operation code” Mnemonic Operation code Functionality SWAP 0x65 temp = reg_buff[1023:0]; reg_buff[1023:0] = reg_buff[2047:1024]; reg_buff[2047:1024] = temp; This instruction swaps/exchanges the two register buffer partitions.
Page 131 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) • 1: block1[127:0] = reg_buff[1*128+127:1*128] • 2: block2[127:0] = reg_buff[2*128+127:2*128] • 3: block3[127:0] = reg_buff[3*128+127:3*128] • 4: block4[127:0] = reg_buff[4*128+127:4*128] • 5: block5[127:0] = reg_buff[5*128+127:5*128] • 6: block6[127:0] = reg_buff[6*128+127:6*128] •...
Page 132 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-11. BLOCK_SET instruction Instruction format BLOCK_SET (size[3:0], dst[3:0], byte[7:0]) Encoding IW[31:24] = “operation code” IW[19:16] = size IW[15:12] = dst IW[7:0] = byte Mnemonic Operation code Functionality BLOCK_SET 0x42 size = (size == 0) ? 16 : size;...
Page 133: Hash Algorithms
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) SetBlock is defined as follows: SetBlock (dst, size, data) { switch (dst) { 0: block0[127:0] = data; 1: block1[127:0] = data; 2: block2[127:0] = data; 3: block3[127:0] = data; 4: block4[127:0] = data;...
Page 134 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) A SHA algorithm calculates a fixed-length hash value from a variable length message. The hash value is used to produce a message digest or signature. It is computationally impossible to change the message without changing the hash value.
Page 135: Sha3
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-14. SHA1 instruction Instruction format SHA1 () Encoding IW[31:24] = “operation code” Mnemonic Operation code Functionality SHA1 0x69 Perform a SHA1 function on a 512-bit message block in reg_buff[511:0] with the current 160-bit hash value in reg_buff[1183:1024].
Page 136: Des And Tdes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) All six hash algorithms are constructed by padding a message M and applying the Keccak-p[1600, 24] permutation repeatedly. The algorithms differ in terms of the rate r and the padding. The permutation’s rate r determines the speed of the algorithm: a higher rate requires less applications of the permutation function (SHA3 instruction).
Page 137 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) (T)DES is supported for backward compatibility. • The DES block cipher encrypts a 64-bit block of plaintext data into a 64-bit block of ciphertext data. • The DES inverse block cipher decrypts a 64-bit block of ciphertext data into a 64-bit block of plaintext data. The DES symmetric key consists of 64 bit.
Page 138 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-20. DES_INV instruction (continued) Instruction format DES_INV () Mnemonic Operation code Functionality DES_INV 0x53 Perform a DES inverse block cipher. • The 64-bit ciphertext is in block0[63:0]. • The resulting 64-bit plaintext is in block1[63:0].
Page 139: Aes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.6 The AES functionality includes a block cipher and an inverse block cipher per the AES standard (FIPS 197): • The block cipher (AES instruction) encrypts a 128-bit block of plaintext data into a 128-bit block of ciphertext data.
Page 140 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) The instructions are described in the following tables. Table 12-24. AES instruction Instruction format AES () Encoding IW[31:24] = “operation code” Mnemonic Operation code Functionality 0x50 Perform an AES block cipher. •...
Page 141: Crc
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.7 The CRC functionality performs a cyclic redundancy check with a programmable polynomial of up to 32 bits. The load FIFO 0 provides the data (and the size of the data) on which the CRC is performed. The data must be laid out in little endian format (least significant byte of a multi-byte word should be located at the lowest memory address of the word).
Page 142 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Load FIFO 0 Single Byte CRC_DATA_CTL.DATA_XOR[] CRC_CTL.DATA_REVERSE Data bit reverse CRC_POL_CTL.POLYNOMIAL[] CRC calculation RESULT.DATA[] (LFSR state) CRC_REM_CTL.DATA_XOR[] CRC_CTL.REM_REVERSE Remainder bit reve CRC_REM_RESULT.REM[] Figure 12-2. CRC functionality The Linear Feedback Shift Register functionality operates on the LFSR state. It uses the programmed polynomial and consumes a data bit for each iteration (eight iterations are performed per cycle to provide a throughput of one data byte per cycle).
Page 143: Prng
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-27. CRC32, CRC16-CCITT, and CRC16 algorithm settings MMIO Register field CRC32 CRC16-CCITT CRC16 CRC_POL_CTL.POLYNOMIAL 0x04c11db7 0x10210000 0x80050000 CRC_CTL.DATA_REVERSE CRC_DATA_CTL.DATA_XOR 0x00 0x00 0x00 RESULT.DATA (seed) 0xffffffff 0xffff0000 0xffff0000 CRC_CTL.REM_REVERSE CRC_REM_CTL.REM_XOR 0xffffffff 0x00000000...
Page 144: Trng
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) LFSR32 output LFSR31 output pseudo random unit LFSR29 output Figure 12-5. XOR reduction logic The pseudo random number generator uses a total of 33 pseudo random bits to generate a result in the range [0, PR_MAX_CTL.DATA[31:0]].
Page 145 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) • After an initial delay, the same ring oscillator will show different oscillation behavior and provides a reliable physical noise source. Therefore, the DAS bits can be dropped during an initialization period (TR_CTL.INIT_DELAY[]). Figure 12-6 gives an overview of the TRNG component.
Page 146 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) RO11: oscillator with 11 inverters RO11_EN output RO15: oscillator with 15 inverters RO15_EN output GARO15: fixed polynomial: x GARO15_EN output FIRO15: fixed polynomial: x FIRO15_EN output Figure 12-8. Four fixed ring oscillators: RO11, RO15, GARO15, FIRO15 The XXX_EN enable signals originate from a MMIO register field.
Page 147 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) output Constant ‘1’ ‘0’ output Figure 12-10. GARO31 “stopped” The programmable polynomial specifies the oscillator feedback. Figure 12-11 illustrates two examples. 7-bit polynomial: x + 1 (POLYNOMIAL = 0x0000:0041 << 24) Constant ‘0’...
Page 148 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) ‘0’ output Constant ‘1’ output Figure 12-13. FIRO31 “stopped” The programmable polynomial specifies the oscillator feedback. Figure 12-14 illustrates two examples. 7-bit polynomial: x + 1 (POLYNOMIAL = 0x0000:0041 << 24) output 31 bit polynomial: x + x + 1 (POLYNOMIAL = 0x04c1:1db7)
Page 149 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) The adaptive proportion test. This test checks for a disproportionate occurrence of a specific bit value (‘0’ or ‘1’) in a bit stream. A detection indicates that a specific active bit value (specified by a status field BIT) has occurred a pre-programmed number of times (specified by a control field CUTOFF_COUNT[15:0]) in a bit sequence of a specific bit window size (specified by a control field WINDOW_SIZE[15:0]).
Page 150: Vector Unit
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) The design uses three Verilog design modules to instantiate the selected cells. This allows easy porting from one standard cell library to another standard cell library. The three Verilog design modules should not be changed by tools (similar to how the platform toolkit components are treated in the design flow).
Page 151 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) • CPU. The VU has CPU-like design components, such as an instruction decoder, a register file, and data path with multiple functional units. The VU architecture is the result of a tradeoff between silicon area, design complexity, performance efficiency, and algorithmic flexibility.
Page 152: Vu Register File
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.10.1 VU register file The register file has sixteen registers (r0 through r15). Each register consists of a 13-bit data field and a 13-bit size field. The data field is either used as: •...
Page 153: Stack
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.10.2 Stack The VU stack resides in the memory region. Register r15 is used as a stack pointer. The stack has two purposes: • It is used to save/restore registers r0 through r14. Each register (data field and size field) uses a single 32-bit word.
Page 154: Memory Operands
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 16 KB Register-file memory region don’t care size[12:0] data[12:0] size[12:0] data[12:0] size[12:0] data[12:0] Figure 12-19. Register file state after FREE_MEM instruction Freeing of stack elements should be in the reverse order of allocation of stack elements. Also see the description of the FREE_MEM instruction for the order in which registers are freed (lower registers are freed before higher registers).
Page 155: Status Register
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Note that the instruction execution time (in clock cycles) is typically independent of the instruction operand data values. However, the execution time is dependent on the size of memory operands (as specified by the register size field).
Page 156: Instructions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.10.6 Instructions The VU instructions operate on either register operand data or memory operand data. Operand types. Typically, VU instruction operands all have the same type: either register or memory operands. However, some exceptions do exist.
Page 157: Instruction Set
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) 12.10.7 Instruction set This section describes all VU instructions. For each instruction, the following is described: • The instruction format – Source operand types (register or memory operands) – Support for conditional execution –...
Page 158 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-31. Instructions with register operand only, Category I Instruction format Mnemonic (rdst, imm13_0[13:0], imm13_1[11:0]) rdst: register operand imm13_0: 13 bit immediate (for register data field) imm13_1: 13-bit immediate (for register size field) Encoding IW[31:30] = “operation code”...
Page 159 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-34. ST_REG instruction Instruction format Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0) rsrc1: register operand rsrc0: register operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[7:4] = rsrc1 IW[3:0] = rsrc0 Mnemonic...
Page 160 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-36. Instructions with register operand only, Category IV Instruction format Mnemonic () or COND_Mnemonic (cc) cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc Mnemonic Operation code Functionality (if “cc”...
Page 161 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-37. Instructions with register operand only, Category V Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: register operand rsrc1: register operand rsrc0: register operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 162 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-39. MOV_STATUS_TO_REG Instruction format Mnemonic (rdst) or COND_Mnemonic (cc, rdst) rdst: register operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[15:12] = rdst Mnemonic Operation code Functionality (if “cc”...
Page 163 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-41. Instructions with mixed operands, Category I Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: register operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 164 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-42. Instructions with mixed operands, Category II Instruction format Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc) rdst: memory buffer operand rsrc: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 165 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-43. Instructions with mixed operands, Category III Instruction format Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc) rdst: memory buffer operand rsrc: register operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 166 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-45. Instructions with mixed operands, Category V Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: register operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 167 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-46. Instructions with memory operands, Category I Instruction format Mnemonic (rdst) or COND_Mnemonic (cc, rdst) rdst: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[15:12] = rdst Shared functionality STATUS.EVEN = (dst_data[0] == 0)
Page 168 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-47. Instructions with memory operands, Category II Instruction format Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc) rdst: memory buffer operand rsrc: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 169 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-48. Instructions with memory operands, Category III Instruction format Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0) rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 170 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-49. Instructions with memory operands, Category IV Instruction format Mnemonic (rsrc) or COND_Mnemonic (cc, rsrc) rsrc: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[3:0] = rsrc Mnemonic Operation code...
Page 171 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-50. Instructions with memory operands, Category V (continued) Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code XMUL...
Page 172 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-50. Instructions with memory operands, Category V (continued) Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code 0x36...
Page 173 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-50. Instructions with memory operands, Category V (continued) Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code SUB_WITH_CARRY...
Page 174 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Cryptographic function block (Crypto) Table 12-51. Instructions with memory operands, Category VI Instruction format Mnemonic (rdst, imm12) or COND_Mnemonic (cc, rdst, imm12) rdst: memory buffer operand rsrc: register operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 175: Program And Debug Interface
The PSoC™ 6 MCU Program and Debug interface provides a communication gateway for an external device to perform programming or debugging. The external device can be a Infineon-supplied programmer and debugger, or a third-party device that supports programming and debugging. The serial wire debug (SWD) or the JTAG interface can be used as the communication protocol between the external device and PSoC™...
Page 176 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface PSoC™ 6 MCU Arm® Cortex®-M0+ subsystem CM0+ AHB decoder CM0 Access Port Cross Trigger CM0 external Cortex®-M0+ Interface (CTI) ROM table Micro Trace Buffer (MTB) SRAM Arm® Cortex®-M4 subsystem CM4 APB decoder CM4 AP Cross Trigger...
Page 177: Debug Access Port (Dap)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface 13.2.1 Debug access port (DAP) The DAP consists of a combined SWD/JTAG interface (SWJ) that also includes the SWD listener. The SWD listener decides whether the JTAG interface (default) or SWD interface is active. Note that JTAG and SWD are mutually exclusive because they share pins.
Page 178: Rom Tables
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface 13.2.2 ROM tables The ROM tables are organized in a tree hierarchy. Each AP has a register that contains a 32-bit address pointer to the base of the root ROM table for that AP. For PSoC™ 6 MCUs, there are three such root ROM tables. Each ROM table contains 32-bit entries with an address pointer that either points to the base of the next level ROM table.
Page 179: Serial Wire Debug (Swd) Interface
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface 13.3 Serial wire debug (SWD) interface The PSoC™ 6 MCU supports programming and debugging through the SWD interface. The SWD protocol is a packet-based serial transaction protocol. At the pin level, it uses a single bidirectional data signal (SWDIO) and a unidirectional clock signal (SWDCK).
Page 180: Swd Timing Details
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface g) The park bit is always logic 1. 2. Target acknowledge response phase: SWDIO driven by the target a) The ACK[2:0] bits represent the target to host response, indicating failure or success, among other results. Table 13-1 for definitions.
Page 181: Turnaround (Trn) Period Details
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface Details on WAIT and FAULT response behaviors are as follows: • For a WAIT response, if the transaction is a read, the host should ignore the data read in the data phase. The target does not drive the line and the host must not check the parity bit as well.
Page 182 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface Boundary Scan Path Boundary Scan Cells IO Pads Core Logic Instruction Register BYPASS Register ID Register Other Register Test Access Port Controller TRST Figure 13-4. JTAG interface architecture The TMS signal controls a state machine in the TAP. The state machine controls which register (including the boundary scan path) is in the TDI-to-TDO shift path, as shown in Figure 13-5.
Page 183 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface TMS = 1 test logic reset TMS = 0 TMS = 0 run test idle TMS = 1 TMS = 1 TMS = 1 select dr scan select ir scan TMS = 0 TMS = 0 TMS = 1...
Page 184: Programming The Psoc™ 6 Mcu
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface 13.5 Programming the PSoC™ 6 MCU The PSoC™ 6 MCU is programmed using the following sequence. See the PSoC™ 6 MCU programming specifications for complete details on the programming algorithm, timing specifications, and hardware configuration required for programming.
Page 185: Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Program and debug interface 13.6 Registers Table 13-3. List of registers Register name Description CM0P_DWT Cortex® M0+ Data Watchpoint and Trace (DWT) registers CM0P_BP Cortex® M0+ BreakPoint (BP) registers CM0P_ROM Cortex® M0+ CPU Coresight ROM table CM0P_CTI Cortex®...
Page 186: Nonvolatile Memory
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Nonvolatile memory This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 187: Flash Geometry
The SFlash region is used to store trim parameters, system configuration parameters, protection and security settings, boot code, and other Infineon proprietary information. Read access to this region is permitted, but program/erase access is limited. The application region is used to store code images or data. The AUXFlash is typically used for EEPROM emulation.
Page 188: Flash Controller
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.1.4 Flash controller Access to the flash memory is enabled through the flash controller. The flash controller interfaces with the AHB- Lite bus and provides flash access for the CM0+, CM4, Crypto, DataWire, and debug. The flash controller generates a bus error if: •...
Page 189: Cpu Caches
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.1.4.3 CPU caches The flash controller provides 8 kB caches for both the CM0+ and CM4 CPUs. Each cache is a four-way set associative with a least recently used (LRU) replacement scheme. Four-way set associativity means that each cache has four ways per set, with each way containing a valid bit, tag, and data.
Page 190: Flash Memory Programming
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.2 Flash memory programming 14.2.1 Features • SROM API library for flash management through system calls such as Program Row, Erase Flash, and Blow eFuse • System calls can be performed using CM0+, CM4, or DAP 14.2.2 Architecture Flash programming operations are implemented as system calls.
Page 191: System Call Implementation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory CM4 or CM0+ A pointer is always used to structure SRAM. Commands that are issued as a single word by DAP can still be issued by CM0+ or CM4, but use an SRAM structure instead. The NMI interrupt handler for system calls works as follows.
Page 192: Srom Api Library
APIs. Table 14-5. List of system calls System call Opcode Description Access allowed category Normal Secure Dead “Infineon ID” 0x00 Returns die ID, CM0+, CM4, CM0+, CM4, CM0+, CM4, page 193 major/minor ID, and protection state “Blow eFuse bit”...
Page 193: System Calls
ID type based on which it will return family ID and revision ID if the ID type is set to ‘0’, and silicon ID and protection state if the ID type is set to ‘1’. Table 14-6. Infineon ID Infineon IDs...
Page 194 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Table 14-6. Infineon ID (continued) Infineon IDs Memory location Data Silicon ID SFlash Silicon ID [15:0] Protection state MMIO Protection [3:0] Parameters if DAP is master Address Value to be written...
Page 195 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if DAP Invoked the system call Address Return value Description IPC_STRUCT_DATA Register Bits [7:0] If ID type = 0, Family ID Lo See the PSoC™ 61 datasheet PSoC™ 62 datasheet If ID type = 1, Silicon ID Lo for silicon ID values for different part numbers.
Page 196 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Address Return value Description Bits [19:16] If ID type = 0, Minor Revision ID If ID type = 1, Protection state 0: UNKNOWN 1: VIRGIN 2: NORMAL 3: SECURE 4: DEAD Bits [23:20] If ID Type = 0 Major Revision ID If ID Type = 1 Life-cycle stage...
Page 197: Blow Efuse Bit
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.2 Blow eFuse bit This function blows the addressed eFuse bit. The read value of a blown eFuse bit is ‘1’ and that of an unblown eFuse bit is ‘0’. These values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Page 198: Read Efuse Byte
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.3 Read eFuse byte This function returns the eFuse contents of the addressed byte. The read value of a blown eFuse bit is ‘1’ and that of an unblown eFuse bit is ‘0’. These values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Page 199: Write Row
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.4 Write row This function is used to program the flash. You must provide data to be loaded and the flash address to be programmed. The WriteRow parameter performs pre-program and erase, and then programs the flash row with contents from the row latch.
Page 200 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Parameters if DAP/CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits [31:24] 0x05...
Page 201: Program Row
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [27:0] Error code (if any) “System call status” on page 220 for details. Bits [31:28] 0xA = SUCCESS/Program Status code (see “System call status”...
Page 202 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Parameters if DAP/CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits[31:24] 0x06...
Page 203: Erase All
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [27:0] Error code (if any) “System call status” on page 220 for details. Bits [31:28] 0xA = SUCCESS/Program Status code (see “System call status”...
Page 204 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Parameters if CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits [31:24] 0x0A...
Page 205: Checksum
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.7 Checksum This function reads either the entire flash or a row of flash, and returns the sum of each byte read. Bytes 1 and 2 of the parameters select whether the checksum is performed on the entire flash or on a row of flash. This function will inherit the identity of the master that called the function.
Page 206: Fmtransitiontolpulp
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [23:0] Checksum Checksum if status is SUCCESS Bits [27:24] 0xXX Not used (don’t care) Bits [31:28] 0xA = SUCCESS Status code (see “System call status”...
Page 207: Compute Hash
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call and SRAM is not used Address Return value Description IPC_STRUCT_DATA Register Bits [31:28] 0xA = SUCCESS Status code 0xF = ERROR Bits [23:0] Error code (if any) Error code 14.5.9 Compute hash...
Page 208: Configureregionbulk
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.10 ConfigureRegionBulk This API writes a 32-bit data value to a set of contiguous addresses. It cannot be used to configure protected registers or flash. The Start and End addresses of the region are configurable but must be within a writable area. The region must also be 32-bit aligned.
Page 209: Directexecute
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.11 DirectExecute This function directly executes code located at a configurable address. This function is only available in normal life-cycle state if the DIRECT_EXECUTE_DISABLE bit is 0. Parameters if DAP is master Address Value to be written Description...
Page 210 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Parameters if DAP/CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits [31:24] 0x14...
Page 211: Soft Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.13 Soft reset This function resets the system by setting CM0+ AIRCR system reset bit. This will result in a system-wide reset, except debug logic. This API can also be used for selective reset of only the CM4 core based on the ‘Type’ parameter.
Page 212: Erase Row
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.14 Erase row This function erases the specified row. You must provide the address of the row that needs to be erased. The values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Page 213: Erase Subsector
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Address Return value Description Bits [27:0] Error code (if any) “System call status” on page 220 for details. Bits [31:28] 0xA = SUCCESS Status code (see “System call status” on page 220 for 0xF = ERROR details).
Page 214: Generatehash
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [23:0] Error code (if any) “System call status” on page 220 for details. Bits [31:28] 0xA = SUCCESS Status code (see “System call status”...
Page 215: Readuniqueid
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.17 ReadUniqueID This function returns the unique ID of the die from SFlash. Parameters if DAP/ CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits[31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address.
Page 216: Checkfactoryhash
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.18 CheckFactoryHash This function generates the FACTORY_HASH according to the TOC1 and compares the value with the FACTORY1_HASH eFuse value. Parameters if DAP is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:24] 0x27...
Page 217: Transitiontorma
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.19 TransitionToRMA This function converts the part from SECURE, SECURE_WITH_DEBUG, or NORMAL to the RMA life-cycle stage. This API performs eFuse programming, VDD should be set to 2.5 V for successful programming. This function uses Flash Boot functions.
Page 218: Readfusebytemargin
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.5.20 ReadFuseByteMargin This API returns the eFuse contents of the addressed byte read marginally. The read value of a blown bit is ‘1’ and of a not blown bit is ‘0’. Parameters if DAP is master Address Value to be written...
Page 219: Transitiontosecure
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory Return if CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [31:28] 0xA = SUCCESS Status code (see “System call status” on page 220 0xF = ERROR for details). Bits [23:0] Byte read from eFuse “System call status”...
Page 220: System Call Status
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Nonvolatile memory 14.6 System call status At the end of every system call, a status code is written over the arguments in the IPC_DATA register or the SRAM address pointed by IPC_DATA. A success status is 0xAXXXXXXX, where X indicates don’t care values or return data for system calls that return a value.
Page 221: Boot Code
TOC1. The FACTORY_HASH is stored in eFuse before the device leaves Infineon. The device validates the FACTORY_HASH as part of the TransitionToSecure system call. The data integrity of selected objects in both TOC1 and TOC2 must be verified as part of authentication of Flash boot by ROM boot in the SECURE life-cycle stage.
Page 222 0x10 Address of Unique ID (fixed size of 12 bytes) stored in SFlash protection state by 0x14 Address of Flash boot object that includes Flash Patch object stored in SFlash Infineon 0x18 Unused 0x1C-0x1F8 Unused CRC16-CCITT (the upper two bytes contain the CRC little endian value and the lower two...
Page 223 Address of First User Application Object 0x14 0x16007C14 TOC2_FIRST_USER_APP_F First Application Object Format (4 bytes). 0 means ORMAT Basic Application Format, 1 means Infineon Secure Application Format, and 2 means Simplified Secure Application Format 0x18 0x16007C18 TOC2_SECOND_USER_APP Address of Second User Application Object (0's if...
Page 224 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code Table 15-3. TOC2_FLAGS bits, default settings, and descriptions TOC2_FLAGS Name Default Description bits value IMO/FLL clock frequency 2 CM0+ clock during boot. This clock will remain at this setting after Flash boot execution until the OEM firmware changes it.
Page 225: Life-Cycle Stages And Protection States
This life-cycle stage allows Failure Analysis (FA). The part is transitioned to the RMA life-cycle stage when the customer wants Infineon to perform failure analysis. The customer erases all sensitive data before invoking the system call that transitions the part to RMA.
Page 226 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code DAP settings for Secure and Dead protection states are set in the SECURE_ACCESS_RESTRICT0 and DEAD_ACCESS_RESTRICT0 registers. DAP settings for the Normal protection state is set in NORMAL_ACCESS_RESTRICTIONS in SFlash. Table 15-7 shows the format used to set the DAP settings for these states.
Page 227 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code Table 15-8. SECURE_ACCESS_RESTRICT1, DEAD_ACCESS_RESTRICT1, and NORMAL_ACCESS_RESTRICTIONS [15:8] Registers (All default to 0) Bits Name Description FLASH_ALLOWED This field indicates what portion of the main flash is accessible through the system debug access port. Only the portion starting at the bottom of flash (0x1000_0000) is exposed to the system DAP.
Page 228: Secure Boot" In Rom Boot
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code As shown in Figure 15-2, if you want to limit the lower fourth of flash of a device with 2MB of flash, write a ‘4’ into the FLASH_ALLOWED field. Only the flash area between 0x10000000 and 0x1007FFFF will be accessible via the SYS_DAP.
Page 229 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code Table 15-10. Region access Region Description CPUSS_BOOT Contains CM0+ protection context 0-3, debug port control, protection status, RAM, and ROM trim control registers. EFUSE_CTL EFUSE_CTL register. Specifies retention for eFuse registers. EFUSE_DATA Contains registers that support life-cycle setting, key storage, and other one-time- programmable data.
Page 230: Swd/Jtag Repurposing
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code Table 15-11. Protection structures (continued) Protection structure Protection Attribute Protected Region Region (Read/Write) settings region base size (Bytes) PERI_MS_PPU_PR2 Disable access ATT0: 1F1F1F1F Entire Crypto 0x4010000 during system ATT1: 1F1F1F1F MMIO region calls with Crypto during any enabled (all...
Page 231 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code RESET Get M4 Reset Vector I am M0+? CM4_VECTOR_TABLE_BASE (CPUSS MMIO) (CPUSS MMIO) Set RST SP Goto RST PC Get M0+ Reset Vector PROTECTION==UNKOWN ? CM0_VECTOR_TABLE_BASE (CPUSS MMIO) (CPUSS MMIO) Set RST SP (Warm Boot Goto RST PC due to CPU...
Page 232: Flash Boot
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code 15.3 Flash boot 15.3.1 Overview The second stage of boot, Flash boot, is entered after ROM boot has authenticated the Flash boot image if the device is in the SECURE or SECURE_WITH_DEBUG life-cycle stage, or if the APP_AUTH_DISABLE field is not set in TOC2.
Page 233: Flash Boot Layout
The Flash boot application version • The number of cores (set to ‘1’ for Flash boot) • CM0+ vector table offset • Infineon ID and CPU Core Index 15.3.4.2 Code segment The CM0 code segment consists of: • CM0+ vector table •...
Page 234: Flash Boot Flow Chart
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code 15.3.5 Flash boot flow chart The Flash boot program flow is shown in Figure 15-5. The entry point is a fixed offset in SFlash. Each section of the flow chart is labeled with an index number. In the sections following the flow chart, explanations of each step are provided with the associated index number.
Page 235: Entry From Rom Boot (0)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code 15.3.5.1 Entry from ROM boot (0) ROM boot transfers control to Flash boot after it validates the SFlash block and TOC1 in the user flash. 15.3.5.2 Basic initialization (1) This stage sets the value of the stack pointer during runtime. To support recovery from Hard-Fault exceptions during Flash boot, this stage also enables interrupts.
Page 236: Is Reset Handler Valid? (6)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code 15.3.5.7 Is reset handler valid? (6) Flash boot checks if the address of the reset handler for the user application is in RAM, SFlash, application flash, or AUXFlash. 15.3.5.8 Authenticate app? (7) Flash boot optionally authenticates a digital signature for the application image if the TOC2_FLAGS bit APP_AUTH_DISABLE = 0.
Page 237: Enable System Calls (10)
Application Format” and the application start address is the start of the user flash. If the TOC2 is valid and the life-cycle stage is NORMAL, then the application can be in either the Basic or Infineon Standard Secure application formats.
Page 238: Set Up Sp (17)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code 15.3.5.18 Set up SP (17) The SP register value for Flash boot is at the top of user RAM. 15.3.5.19 Idle loop (18) Before going to an idle loop the Flash boot sets the CPUSS_CM0_VECTOR_TABLE_BASE MMIO register to 0xFFFF_0000.
Page 239: Protection = Virgin? (31)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Boot code Table 15-12. Error code (continued) Error name Value Description CY_FB_ERROR_BOOT_LIN_INIT 0xF100_0141 Bootloader error, LIN initialization failed CY_FB_ERROR_BOOT_LIN_SET_CMD 0xF100_0142 Bootloader error, LinSetCmd() failed 15.3.5.21 Protection = Virgin? (31) The CPUSS_PROTECTION MMIO register value is compared to the desired protection mode. 15.3.5.22 Life cycle = SECURE (32) The life-cycle stage value is stored in eFuse.
Page 240: Efuse Memory
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture eFuse memory eFuse memory This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 241 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture eFuse memory Table 16-1. PSoC™ 6 MCU eFuse byte assignments (continued) Offset No. of Name Description bytes Unused Not used CY_ASSET_HASH, Similar to the factory hash, but it does not CY_ASSET_HASH_ZEROS include trim values so it will be the same for all parts with the same silicon and firmware version.
Page 242: Device Security
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device security Device security This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 243 • VIRGIN – This stage is used by Infineon during assembly and testing. During this stage, trim values and flash boot are written into SFlash. Devices that are in this stage never leave the factory. In this stage, the boot ROM assumes that no other eFuse data or flash data is valid.
Page 244 When invoking the system call to transition to RMA, the customer must provide a certificate that authorizes Infineon to transition the device with a specific Unique ID to the RMA life cycle stage. The certificate will be signed by the customer using the same private key that is used to sign the user application image. The verification of the signature uses the same algorithm used by flash boot to authenticate the user application.
Page 245 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device security UNKNOWN (After Reset) VIRGIN eFuse Lifecycle Bits Set? NORMAL Lifecycle in NORMAL eFuse SECURE Lifecycle in SECURE eFuse Corruption or error detected during the boot process DEAD Figure 17-2. Protection state transitions Protection state is defined by the STATE field of the CPUSS_PROTECTION register.
Page 246: Flash Security
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device security 17.2.2 Flash security PSoC™ 6 MCUs include a flexible flash-protection system that controls access to flash memory. This feature is designed to secure proprietary code, but it can also be used to protect against inadvertent writes to the bootloader portion of flash.
Page 247: System Resources Subsystem (Srss)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture System resources subsystem (SRSS) Section C: System resources subsystem (SRSS) This section encompasses the following chapters: • “Power supply and monitoring” on page 248 • “Device power modes” on page 256 • “Backup system” on page 270 •...
Page 248: Power Supply And Monitoring
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring Power supply and monitoring This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 249: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring 18.2 Architecture 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF SS_NS DD_NS BACKUP DDIO SSIO PSoC™ 6 MCU On-chip Low-dropout regulator Flash...
Page 250: Power Supply
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring 18.3 Power supply 18.3.1 Regulators summary 18.3.1.1 Core regulators The device includes the following core regulators to power peripherals and blocks in various power modes. Linear core regulator The device includes a linear LDO regulator to power the Active and Sleep mode peripherals. This regulator generates the core voltage (V ) required for Active mode operation of the peripherals from V .
Page 251 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring 3. Reduce the device current consumption by reducing clock frequency and switching off blocks to meet the buck regulator’s load capacity. 4. Disable System Deep Sleep mode regulators. Because the buck regulator is available in the System Deep Sleep power mode, other deep-sleep regulators can be powered down.
Page 252: Power Pins And Rails
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring 18.3.2 Power pins and rails Table 18-1 lists all the power supply pins available in the device. The supply rails running inside the device , and V ) are derived from these external supply pins/rails. CCDPSLP CCRET DDBAK...
Page 253: Power-On Reset (Por)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring 18.4.1 Power-on reset (POR) POR circuits provide a reset pulse during the initial power ramp. POR circuits monitor V voltage. Typically, the POR circuits are not very accurate about the trip-point. POR circuits are used during initial chip power-up and then disabled.
Page 254: Overvoltage Protection (Ovp)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring FALLING(2) or BOTH(3). Firmware can workaround this condition by disabling falling edge detection before entering Deep Sleep, and re-enabling it after exiting Deep Sleep. 4. Enable the LVD by setting the HVLVD1_EN bit in the PWR_LVD_CTL register. This may cause a false LVD event. 5.
Page 255: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Power supply and monitoring 18.5 Register list Table 18-2. Register list Name Description PWR_CTL Power Mode Control register - controls the device power mode options and allows observation of current state PWR_BUCK_CTL Buck Control register - controls the buck output and master buck enable PWR_LVD_CTL LVD Configuration register SRSS_INTR...
Page 256: Device Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes Device power modes This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 257 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes The SysPm peripheral driver library (PDL) driver supports all device power mode transitions and is the recommended method of transition and configuration of PSoC™ 6 MCU power resources. Table 19-1 summarizes the power modes available in PSoC™...
Page 258 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes Table 19-1. PSoC™ 6 MCU power modes (continued) System Description Entry conditions Wakeup Wakeup power power sources action mode mode Active 0.9 V core voltage. All Manual register write from peripherals are available system LP mode.
Page 259: Cpu Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.2.1 CPU power modes The CPU Active, Sleep, and Deep Sleep modes are the standard Arm®-defined power modes supported by both Cortex®-M4 and Cortex®-M0+ CPUs. All Arm® CPU power modes are available in both system LP and ULP power modes.
Page 260: System Deep Sleep Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.2.3 System Deep Sleep mode In system Deep Sleep mode, all the high-speed clock sources are off. This in turn makes high-speed peripherals unusable in system Deep Sleep mode. However, low-speed clock sources and peripherals may continue to operate, if configured and enabled by the firmware.
Page 261: Other Operation Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes some content. Note that these registers are reset by other reset events. On a Hibernate wakeup event, the HIBERNATE bit [31] of the PWR_HIBERNATE register is cleared. The brownout detect (BOD) block is not available in Hibernate mode. As a result, the device does not recover from a brownout event in Hibernate mode.
Page 262: Power Mode Transitions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.3 Power mode transitions Figure 19-1 shows various states the device can be in along with possible power mode transition paths. O ff X R E S /P O R / X R E S /P O R /B O D X R E S B O D...
Page 263: Power-Up Transitions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.3.1 Power-up transitions Table 19-2 summarizes various power-up transitions, their type, triggers, and actions. Table 19-2. Power mode transitions Initial Final Type Trigger Actions state state XRES External Power rail (V ) ramps up 1.
Page 264: Power Mode Transitions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.3.2 Power mode transitions Table 19-3. Power mode transitions Initial Final Type Trigger Actions state state System LP System Internal Firmware action 1. Device is put into 1. Ensure the Clk_HF paths, peripheral, and slow ULP mode with all clocks are less than the ULP clock speed limitations.
Page 265 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes Table 19-3. Power mode transitions (continued) Initial Final Type Trigger Actions state state System System Internal Firmware action 1. CPU clocks are LP/ULP LP/UP Perform these steps to enter Deep Sleep mode gated off and CPU and CPU...
Page 266 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes Table 19-3. Power mode transitions (continued) Initial Final Type Trigger Actions state state System System Internal Hardware action 1. High-frequency LP/ULP Deep 1. When both CPUs enter CPU Deep Sleep mode and clocks are shut and CPU Sleep...
Page 267: Wakeup Transitions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.3.3 Wakeup transitions Table 19-4. Wakeup transitions Initial Final state Type Trigger Actions state CPU Sleep CPU Active Internal/ Any peripheral 1. Clock to CPU is ungated. External interrupt masked 2.
Page 268: Summary
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.4 Summary Table 19-5. Resources available in different power modes Component Power modes Deep Sleep Hibernate XRES Power off with CPU Sleep/ CPU Sleep/ backup Active Deep Sleep Active Deep Sleep Core functions Sleep Sleep...
Page 269: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Device power modes 19.5 Register list Table 19-6. Register list Name Description PWR_CTL Power Mode Control register – controls the device power mode options and allows observation of current state PWR_HIBERNATE Hibernate Mode register – controls various Hibernate mode entry/exit related options PWR_HIB_DATA Hibernate Mode Data register –...
Page 270: Backup System
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system Backup system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 271: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system 20.2 Architecture AHB-Lite Bus (Power Supply Pins) User Registers RTC Registers AHB Interface Backup DDBAK Power Switch BACKUP MMIO Alarm Alarm Interface Config Config PMIC_Wakeup_In Backup Watch Crystal PMIC_Wakeup_Out Registers Oscillator (32 bytes) (WCO) (Controls an External...
Page 272: Clocking
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system Note: If V and V are connected on the PCB, the Backup domain may require an explicit reset triggered BACKUP by firmware using the RESET bitfield in the BACKUP_RESET register. This firmware reset is required if the V supply was invalid during a previous power supply ramp-up or brownout event.
Page 273: Calibration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system formed by connecting a 220-pF/6-V capacitor between WCO_IN and ground, and a 2.2-pF/ 200-V capacitor between WCO_IN and the 60-Hz/120-V mains input. The PRESCALER bitfield in BACKUP_CTL must be configured for a prescaler value of 60. •...
Page 274: Reading Rtc User Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system BCD encoding indicates that each four-bit nibble represents one decimal digit. Constant bits are omitted in the RTC implementation. For example, the maximum RTC_SEC is 59, which can be represented as two binary nibbles 0101b 1001b.
Page 275: Alarm Feature
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system 20.7 Alarm feature The Alarm feature allows the RTC to be used to generate an interrupt, which may be used to wake up the system from Sleep, Deep Sleep, and Hibernate power modes. The Alarm feature consists of six fields corresponding to the fields of the RTC: Month/Date, Day-of-Week, and Hour : Minute : Second.
Page 276: Pmic Control
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system The BACKUP_INTR_MASK register can be used to disable certain interrupts from the backup system. Table 20-3. Interrupt mask bits Bit name Description ALARM1 Mask bit for interrupt generated by ALARM1 ALARM2 Mask bit for interrupt generated by ALARM2 CENTURY Mask bit for century interrupt (interrupt generated when the Year field rolls over from 99 to...
Page 277: Backup Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Backup system When the PMIC_EN bit is cleared by firmware, the external PMIC is disabled and the system functions normally until V is no longer present (OFF with Backup mode). The firmware can set this bit if it does so before V actually removed.
Page 278: Clocking System
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system Clocking system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 279: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 21.2 Architecture Figure 21-1 gives a generic view of the clocking system in PSoC™ 6 MCUs. Path Mux Root Clock mux (Clks_HF[i] are Root Clocks) (FLL/PLLs) Clock CLK_HF[0] Predivider (1/2/4/8) CM0+ clk_peri Clock EXTCLK...
Page 280: Eco Trimming
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 21.3.2.1 ECO trimming The ECO supports a wide variety of crystals and ceramic resonators with the nominal frequency range specification of f = 16 MHz – 35 MHz. The crystal manufacturer typically provides numerical values for parameters, namely the maximum drive level (DL), the maximum equivalent series resistance (ESR), shunt capacitance of the crystal (C ), and the parallel load capacitance (C...
Page 281: Watch Crystal Oscillator (Wco)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system The ILO can be used as the clock source for CLK_LF, which in turn can be used as a source for the backup domain (CLK_BAK). CLK_BAK runs the real-time clock (RTC). This can be useful if you do not wish to populate a WCO. Although the ILO is not suitable as an RTC due to its poor accuracy, it can be used as a HIBERNATE wakeup source using the wakeup alarm facility in the RTC.
Page 282: Frequency Lock Loop (Fll)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system a) PFD frequency (phase detector frequency). f / REFERENCE_DIV. It must be in the range 4 MHz to 8 MHz. There may be multiple reference divider values that meet this constraint. b) VCO frequency.
Page 283 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system Within each range, the CCO output is controlled via a 9-bit trim field. This trim field is updated via hardware based on the control algorithm described below. A reference clock must be provided to the FLL. This reference clock is typically the IMO, but could be many different clock sources.
Page 284: Configuring The Fll
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system error of 4 percent from the desired 100 MHz. Therefore, the best way to improve this is to increase REF_DIV. However, the larger REF_DIV is, the longer each measurement cycle takes, thus increasing the lock time. In this example, REF_DIV was set to 146.
Page 285 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 4. Set FLL_MULT in CLK_FLL_CONFIG. FLL_MULT is the ratio between the desired CCO frequency and the divided input frequency. This is the ideal value for the counter that counts the number of CCO clocks in one period of the divided input frequency. ...
Page 286 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 1. Set LOCK_TOL in CLK_FLL_CONFIG2. LOCK_TOL determines how much error the FLL can tolerate at the output of the counter that counts the number of CCO clocks in one period of the divided reference clock. A higher tolerance can be used to lock more quickly or track a less accurate source.
Page 287: Enabling And Disabling The Fll
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system The lock time depends on the time for each adjustment step in the locking process; Step_Time = (N / f ) + (SETTLING_COUNT / f Multiply this number by the number of steps it takes to lock, to determine lock time. Typically, the FLL locks within the first ~10 steps.
Page 288: High-Frequency Root Clocks
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system Table 21-9. Clock path source selections Name Description PATH_MUX[2:0] Selects the source for clk_path[i] 0: IMO 1: EXTCLK 2: ECO 3: Reserved4: DSI_MUX 5-7: Reserved The DSI mux is configured through the CLK_DSI_SELECT[i] register. Table 21-10.
Page 289: Medium-Frequency Clock
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system Each CLK_HF has a pre-divider, which is set in the CLK_ROOT_SELECT register. Table 21-13. HFCLK divider selection Name Description ROOT_DVI[5:4] Selects predivider value for the clock root 0: No Divider 1: Divide clock by 2 2: Divide clock by 4 3: Divide clock by 8 CLK_HF[1-4] can be enabled and disabled.
Page 290: Group Clocks (Clk_Sys)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 21.5.6 Group clocks (clk_sys) On the PSoC™ 6 platform, peripherals are grouped. Each group has a dedicated group clock (also referred to as clk_sys). The group clock sets the clock rate for the AHB interface on the peripheral; it also sets the clock rate for the trigger outputs and trigger input synchronization.
Page 291: Peripheral Clock Dividers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 21.7 Peripheral clock dividers The PSoC™ 6 MCU peripherals such as SCBs and TCPWMs require a clock. These peripherals can be clocked only by a peripheral clock divider. The PSoC™ 6 MCU has 15 peripheral clock dividers (PCLK). It has four 8-bit dividers, eight 16-bit dividers, two fractional 16.5-bit dividers (16 integer bits, five fractional bits), and one 24.5-bit divider (24 integer bits, five fractional bits).
Page 292 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system These clock signals may or may not be acceptable, depending on the logic functionality implemented on these two clocks. If the two clock domains communicate with each other, and the slower clock domain (12 MHz) assumes that each high/‘1’...
Page 293: Connecting Dividers To Peripheral
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 21.7.2.2 Connecting dividers to peripheral The PSoC™ 6 MCU has 28 peripherals, which can connect to one of the programmable dividers. Table 21-15 lists those peripherals. Table 21-15. Clock dividers to peripherals Clock number Destination scb[0].clock...
Page 294: Clock Calibration Counters
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Clocking system 21.8 Clock calibration counters A feature of the clocking system in PSoC™ 6 MCUs is built-in hardware calibration counters. These counters can be used to compare the frequency of two clock sources against one another. The primary use case is to take a higher accuracy clock such as the ECO and use it to measure a lower accuracy clock such as the ILO.
Page 295: Reset System
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Reset system Reset system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 296 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Reset system Table 22-1 lists all the reset sources in the PSoC™ 6 MCU. Table 22-1. PSoC™ 6 MCU reset sources Reset source Reset condition Availability in Cause detection system power modes Power-on reset This reset condition occurs during Not inferable using the reset cause device power-up.
Page 297: Power-On Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Reset system 22.2.1 Power-on reset Power-on reset is provided to keep the system in a reset state during power-up. POR holds the device in reset until the supply voltage, V reaches the datasheet specification. The POR activates automatically at power-up. See the PSoC™...
Page 298: Logic Protection Fault Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Reset system 22.2.6 Logic protection fault reset Logic protection fault reset detects any unauthorized protection violations and causes the device to reset if they occur. One example of a protection fault is reaching a debug breakpoint while executing privileged code. The RESET_ACT_FAULT or RESET_DPSLP_FAULT bits of the RES_CAUSE register is set when a protection fault occurs in Active or Deep Sleep modes, respectively.
Page 299: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Reset system Table 22-2. Reset cause bits to detect reset source (continued) Register Bitfield Number Description of bits RES_CAUSE RESET_DPSLP_FAULT Fault logging system requested a reset from its Deep Sleep logic. RES_CAUSE RESET_CSV_WCO_LOSS 1 Clock supervision logic requested a reset due to loss of a watch-crystal clock.
Page 300: O System
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system I/O system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 301: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.2 Architecture The PSoC™ 6 MCU is equipped with analog and digital peripherals. Figure 23-1 shows an overview of the routing between the peripherals and pins. GPIO & Port UDB Array Control Fixed Function CAPSENSE™...
Page 302: I/O Cell Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.2.1 I/O cell architecture Figure 23-2 shows the I/O cell architecture present in every GPIO cell. It comprises an input buffer and an output driver that connect to the HSIOM multiplexers for digital input and output signals. Analog peripherals connect directly to the pin for point to point connections or use the AMUXBUS.
Page 303: Digital Input Buffer
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.2.2 Digital input buffer The digital input buffer provides a high-impedance buffer for the external digital input. The buffer is enabled or disabled by the IN_EN[7:0] bit of the Port Configuration Register (GPIO_PRTx_CFG, where x is the port number). The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripherals.
Page 304 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-1. Drive mode settings Drive mode Value CPU Register, AMUXBUS, UDB/DSI Fixed-function digital peripheral digital peripheral OUT_EN = 1 OUT_EN = 0 OUT_EN = 1 OUT_EN = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 High impedance HI-Z HI-Z...
Page 305 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system DDIO DDIO DDIO OUT_EN OUT_EN OUT_EN OUT_EN High Impedance Reserved Resistive Resistive Pull up Pull down DDIO DDIO DDIO DDIO OUT_EN OUT_EN OUT_EN OUT_EN Open Drain, Open Drain, Strong Resistive Pull Up Drives Low Drives High and Down...
Page 306: Slew Rate Control
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system • Resistive pull-up and resistive pull-down In the resistive pull-up and pull-down mode, the GPIO will have a series resistance in both logic 1 and logic 0 output states. The high data state is pulled up while the low data state is pulled down. This mode is useful when the pin is driven by other signals that may cause shorts.
Page 307 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-2. HSIOM connections (continued) SELy_SEL Name Digital driver signal Digital input Analog Description source signal switches destination OUT_EN AMUX AMUX DSI_GPIO DSI OUT DSI IN DSI controls OUT, Register GPIO_PRTx_OUT register controls OUT_EN AMUXA IN Register...
Page 308 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-2. HSIOM connections (continued) SELy_SEL Name Digital driver signal Digital input Analog Description source signal switches destination OUT_EN AMUX AMUX DS_3 Deep Deep Sleep Deep Sleep Deep Sleep functionality 3 - Sleep Source See the datasheet for specific...
Page 309: I/O State On Power Up
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-2. HSIOM connections (continued) SELy_SEL Name Digital driver signal Digital input Analog Description source signal switches destination OUT_EN AMUX AMUX DS_4 Deep Deep Sleep Deep Sleep Deep Sleep functionality 4 - Sleep Source See the datasheet for specific...
Page 310: Behavior In Low-Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.5 Behavior in low-power modes Table 23-3 shows the status of GPIOs in low-power modes. Table 23-3. GPIO in low-power modes Low-power Status mode • Standard GPIO, GPIO-OVT, and SIO pins are active and can be driven by most peripherals CPU Sleep such as CAPSENSE™, TCPWMs, and SCBs, which can operate in CPU Sleep mode.
Page 311 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Edge Detector 50 ns Glitch Filter Pin 0 Edge Detector Pin 1 Edge Detector Pin 2 Edge Detector Pin 3 Edge Detector Interrupt Signal Pin 4 Edge Detector Pin 5 Edge Detector Pin 6 Edge Detector Pin 7...
Page 312: Peripheral Connections
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system When a port pin edge occurs, you can read the Port Interrupt Status register, GPIO_PRTx_INTR, to know which pin caused the edge. This register includes both the latched information on which pin detected an edge and the current pin status.
Page 313: Analog I/O
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.8.2 Analog I/O Analog resources, such as LPCOMP, SAR ADC, and CTB, which require low-impedance routing paths have dedicated pins. Dedicated analog pins provide direct connections to specific analog blocks. They help improve performance and should be given priority over other pins when using these analog resources.
Page 314: Smart I/O
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.9 Smart I/O The Smart I/O block adds programmable logic to an I/O port. This programmable logic integrates board-level Boolean logic functionality such as AND, OR, and XOR into the port. A graphical interface is provided with the ModusToolbox™...
Page 315: Clock And Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.9.2.1 Clock and reset The clock and reset component selects the Smart I/O block’s clock (clk_block) and reset signal (rst_block_n). A single clock and reset signal is used for all components in the block. The clock and reset sources are determined by the CLOCK_SRC[4:0] bitfield of the SMARTIO_PRTx_CTL register.
Page 316: Synchronizer
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-6. Clock and Reset Register control Register[BIT_POS] Bit name Description SMARTIO_PRTn_CTL[ CLOCK_SRC[4:0] Clock (clk_block)/reset (rst_block_n) source selection: 12:8] 0: io_data_in[0]/1 7: io_data_in[7]/1 8: chip_data[0]/1 15: chip_data[7]/1 16: clk_smartio/rst_sys_act_n; asserts reset in any power mode other than System LP or ULP;...
Page 317: Lookup Table (Lut)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.9.2.3 Lookup table (LUT) Each Smart I/O block contains eight lookup table (LUT) components. The LUT component consists of a three- input LUT and a flip-flop. Each LUT block takes three input signals and generates an output based on the configuration set in the SMARTIO_PRTx_LUT_CTLy register (y denotes the LUT number).
Page 318 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-7. LUT Register control (continued) Register[BIT_POS] Bit name Description SMARTIO_PRTx_LUT_SELy[3:0] LUT_TR0_SEL[3:0] LUT input signal “tr0_in” source selection: 0: Data unit output 1: LUT 1 output 2: LUT 2 output 3: LUT 3 output 4: LUT 4 output 5: LUT 5 output 6: LUT 6 output...
Page 319 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system Table 23-7. LUT Register control (continued) Register[BIT_POS] Bit name Description SMARTIO_PRTx_LUT_SELy[11:8] LUT_TR1_SEL[3:0] LUT input signal “tr1_in” source selection: 0: LUT 0 output 1: LUT 1 output 2: LUT 2 output 3: LUT 3 output 4: LUT 4 output 5: LUT 5 output 6: LUT 6 output...
Page 320: Data Unit (Du)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system OPC[1:0] = 0 tr0_in tr1_in tr_out tr2_in LUT[7:0] OPC[1:0] = 1 tr0_in tr1_in tr_out tr2_in clk_block LUT[7:0] OPC[1:0] = 2 tr0_in tr1_in tr_out tr2_in clk_block LUT[7:0] OPC[1:0] = 3 LUT[5] Enable LUT[4] tr2_in LUT[3]...
Page 321 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system The trigger signals are selected using the DU_TRx_SEL[3:0] bitfield of the SMARTIO_PRTx_DU_SEL register. The DUT_DATAx_SEL[1:0] bits of the SMARTIO_PRTx_DU_SEL register select the 8-bit input data source. The size of the DU (number of bits used by the datapath) is defined by the DU_SIZE[2:0] bits of the SMARTIO_PRTx_DU_CTL register.
Page 322 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system mask = (2 ^ (DU_SIZE+1) – 1) data_eql_data1_in = (data & mask) == (data1_in & mask)); data_eql_0 = (data & mask) == 0); data_incr = (data + 1) & mask; data_decr = (data - 1) &...
Page 323 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system else if (tr1_in) data <= data_eql_data1_in ? data0_masked : data_incr; else if (tr2_in) data <= data_eql_0 ? data0_masked : data_decr; // ROR operation: rotates data right and LSb is sent out. The data for rotation is taken from // data0.
Page 324: Routing
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system if (tr0_in) data <= data0_masked; 23.9.3 Routing The Smart I/O block includes many switches that are used to route the signals in and out of the block and also between various components present inside the block. The routing switches are handled through the PRTGIO_PRTx_LUT_SELy and SMARTIO_PRTx_DU_SEL registers.
Page 325 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system is bypassed to the HSIOM signal path directly – Smart I/O logic will not be present in that signal path. This is useful when the Smart I/O function is required only on select I/Os. b) Pipelined trigger mode: The LUT input multiplexers and the LUT component itself do not include any combinatorial loops.
Page 326: Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture I/O system 23.10 Registers Table 23-10. I/O Registers Name Description GPIO_PRTx_OUT Port output data register reads and writes the output driver data for I/O pins in the port. GPIO_PRTx_OUT_CLR Port output data clear register clears output data of specific I/O pins in the port. GPIO_PRTx_OUT_SET Port output data set register sets output data of specific I/O pins in the port.
Page 327: Watchdog Timer
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer Watchdog timer This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 328: Free-Running Wdt
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer Device Interrupt CFG/STATUS Registers Free running watchdog timer Clock Reset CFG/STATUS Interrupt Multi counter watchdog timers (x2) Device Reset frequency Clock clock (LFCLK) Reset Figure 24-1. Watchdog timer block diagram 24.3 Free-running WDT 24.3.1 Overview...
Page 329 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer When enabled, the WDT counts up on each rising edge of the ILO. When the counter value (WDT_CNT register) equals the match value stored in MATCH bits [15:0] of the WDT_MATCH register, an interrupt is generated. The match event does not reset the WDT counter and the WDT keeps counting until it reaches the 16-bit boundary (65535) at which point, it wraps around to 0 and counts up.
Page 330: Watchdog Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer Table 24-1. Free-running WDT configuration options (continued) Register [Bit_Pos] Bit_Name Description SRSS_INTR[0] WDT_MATCH WDT interrupt request This bit is set whenever a watchdog match event happens. The WDT interrupt is cleared by writing a ‘1’ to this bit SRSS_INTR_MASK[0] WDT_MATCH Mask for the WDT interrupt 0: WDT interrupt is blocked...
Page 331: Watchdog Interrupt
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.3.3 Watchdog interrupt In addition to generating a device reset, the WDT can be used to generate interrupts. Note that interrupt servicing and watchdog reset cannot be used simultaneously using the free-running WDT. The watchdog counter can send interrupt requests to the CPU in CPU Active power modes and to the wakeup interrupt controller (WIC) in CPU Sleep and Deep Sleep power modes.
Page 332: Multi-Counter Wdts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.4 Multi-counter WDTs 24.4.1 Overview Figure 24-3 shows the functional overview of a single multi-counter WDT block. The PSoC™ 6 MCU has two MCWDT blocks. Each MCWDT block includes two 16-bit counters (MCWDTx_WDT0 and MCWDTx_WDT1) and one 32-bit counter (MCWDTx_WDT2).
Page 333: Mcwdtx_Wdt0 And Mcwdtx_Wdt1 Counters Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.4.1.1 MCWDTx_WDT0 and MCWDTx_WDT1 counters operation MCWDTx_WDT0 and MCWDTx_WDT1 are 16-bit up counters, which can be configured to be a 16-bit free-running counter or a counter with any 16-bit period. These counters can be used to generate an interrupt or reset. The WDT_CTR0 bits [15:0] and WDT_CTR1 bits [16:31] of the MCWDTx_CNTLOW register hold the current counter values of MCWDTx_WDT0 and MCWDTx_WDT1 respectively.
Page 334 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer Table 24-2. MCWDTx_WDT0 and MCWDTx_WDT1 configuration options Register [Bit_Pos] Bit_Name Description MCWDTx_CONFIG[1:0] WDT_MODE0 WDT action on a match event (WDT_CTRx == WDT_MATCHx) MCWDTx_CONFIG[9:8] WDT_MODE1 0: Do nothing 1: Assert interrupt (WDT_INTx) 2: Assert device reset 3: Assert interrupt on match and a device reset on the third unhandled interrupt...
Page 335: Mcwdtx_Wdt2 Counter Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.4.1.2 MCWDTx_WDT2 counter operation The MCWDTx_WDT2 is a 32-bit free-running counter, which can be configured to generate an interrupt. The MCWDTx_CNTHIGH register holds the current value of the MCWDTx_WDT2 counter. MCWDTx_WDT2 does not support a match feature.
Page 336: Enabling And Disabling Wdt
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.4.2 Enabling and disabling WDT The MCWDT counters are enabled by setting the WDT_ENABLEx bit in the MCWDTx_CTL register and are disabled by clearing it. Enabling or disabling a MCWDT requires 1.5 LFCLK cycles to come into effect. Therefore, the WDT_ENABLEx bit value must not be changed more than once in that period and the WDT_ENABLEDx bit of the MCWDTx_CTL register can be used to monitor enabled/disabled state of the counter.
Page 337: Watchdog Cascade Options
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.4.3 Watchdog cascade options The cascade configuration shown in Figure 24-3 provides an option to increase the MCWDT counter resolution. The WDT_CASCADE0_1 bit [3] of the MCWDTx_CONFIG register cascades MCWDTx_WDT0 and MCWDTx_WDT1 and the WDT_CASCADE1_2 bit [11] of the MCWDTx_CONFIG register cascades MCWDTx_WDT1 and MCWDTx_WDT2.
Page 338 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer LFCLK WDT_RESET0 First reset Second reset to issued to correct the both behavior counters WDT_RESET1 ~100 µs 0x001F 0x0020 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 WDT_CTR0 WDT_CTRx == WDT_MATCHx 0x0000 0x0001 0x0000 WDT_CTR1 Counter...
Page 339: Mcdwt Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 24.4.4 MCDWT reset MCWDTx_WDT0 and MCWDTx_WDT1 can be configured to generate a device reset similar to the free-running WDT reset. Note that when the debug probe is connected, the device reset is blocked but an interrupt is generated if configured.
Page 340: Reset Cause Detection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Watchdog timer 7. Enable MCWDTx interrupt to the CPU by configuring the appropriate ISER register. See the “Interrupts” page 61. 8. In the ISR, clear the WDTx interrupt by setting the WDT_INTx bit in the MCWDTx_INTR register. Note that interrupts from all three WDTx counters of the MCWDT block are mapped as a single interrupt to the CPU.
Page 341: Trigger Multiplexer Block
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Trigger multiplexer block Trigger multiplexer block This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 342: Trigger Multiplexer Group
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Trigger multiplexer block 25.2.1 Trigger multiplexer group The trigger multiplexer block is implemented using several trigger multiplexers. A trigger multiplexer selects a signal from a set of trigger output signals from different peripheral blocks to route it to a specific trigger input of another peripheral block.
Page 343 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Trigger multiplexer block Trigger Mux Group 0 SW Input 1 [0] Cpuss.Zero Trigger 1-to-1 Group 0 [1:8] DW0 Tr_out[0:7] [9:16] DW1 Tr_out[0:7] [17:28] *TCPWM0 (32-bit) [29:52] Tr_overflow[0:3] DW0 tr_in[16:27] Tr_compare_match[0:3] DW0 Tr_in[0:7] 12 [53:64] tr_tx_req[0:5] Tr_underflow[0:3] tr_rx_req[0:5]...
Page 344: Software Triggers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Trigger multiplexer block Trigger Mux Group 0 [17] Tr_overflow[0] [18] Tr_compare_match[0] [19] TCPWM0(32-bit) Tr_underflow[0] Tr_overflow[0:3] 12 [17:28] Tr_compare_match[0:3] [26] Tr_underflow[0:3] Tr_overflow[3] [27] Tr_compare_match[3] [28] Tr_underflow[3] Trigger Mux Group 2 [61] Tr_i2c_scl_filtered[0] [62] Tr_tx_req[0] [63] Tr_rx_req[0] Tr_i2c_scl_filtered[0:6]...
Page 345: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Trigger multiplexer block 25.3 Register list Table 25-1. Register list Register name Description PERI_TR_CMD Trigger command register. The control enables software activation of a specific input trigger or output trigger of the trigger multiplexer structure.
Page 346 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Trigger multiplexer block Table 25-2. Trigger group Trigger group number Description Routes all input trigger signals to DMA0 Routes all input trigger signals to DMA1 Routes all input trigger signals to TCPWM0(32-bit) Routes all input trigger signals to TCPWM1(16-bit) Routes all input trigger signals to HSIOM Routes all input trigger signals to CPUSS CTI Routes all input trigger signals to DMAC...
Page 347: Digital Subsystem
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Digital subsystem Section D: Digital subsystem This section encompasses the following chapters: • “Secure digital host controller (SDHC)” on page 348 • “Serial Communications Block (SCB)” on page 362 • “Serial memory interface (SMIF)” on page 427 •...
Page 348: Secure Digital Host Controller (Sdhc)
(eMMC)-based memory devices, secure digital (SD) cards, and secure digital input output (SDIO) cards. The block supports all three interfaces – SD, SDIO, and eMMC. The block can also work with devices providing SDIO interface, such as Infineon' WiFi products (for example, CYW4343W). Figure 26-1 illustrates a typical application using the SDHC block.
Page 349: Features Not Supported
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.1.1 Features not supported The SDHC block does not support the following features. • SD/SDIO operation in UHS-II mode • Command queuing engine (CQE) • eMMC boot operation in dual data rate mode •...
Page 350: Clocking
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.3 Clocking Table 26-1 lists the different clocks used in the SDHC block. While configuring the clock for SDHC make sure that clk_slow  clk_sys  clk_card. Table 26-1. Clocks in SDHC Source SDHC clock Function...
Page 351: Timeout (Tout) Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) These fields are set automatically, based on the selected Bus Speed mode, to a value specified in one of the preset registers when HOST_CTRL2_R.PRESET_VAL_ENABLE is set. The preset registers are selected according to Table 26-2.
Page 352: Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.5 Power modes The block can operate during active and sleep system power modes. It does not support deep sleep mode and cannot wake up from events such as card insertion and removal when the system is in deep sleep. All the core registers except the packet buffer SRAM are retained when the system enters deep sleep mode and the SRAM is switched off to save power.
Page 353: Sdio Interrupt
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) Following is the list of registers used in interrupt configuration. Table 26-3. Interrupt Control Registers Register Description WUP_CTRL_R Enables or disables different wakeup interrupts. Host driver must maintain voltage on the SD bus by setting PWR_CTRL_R.SD_BUS_PWR_VDD1 bit for these interrupts to occur.
Page 354: Switching Signaling Voltage From 3.3 V To 1.8 V
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) Table 26-4. I/O signal interface (continued) Signal Function Register configuration io_volt_sel Signaling voltage select output (see GP_OUT_R.IO_VOLT_SEL_OE “Switching signaling voltage from 3.3 V to 1.8 V” on page 354) card_if_pwr_en Card interface power enable output GP_OUT_R.CARD_IF_PWR_EN_OE...
Page 355: Dma Engine
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.9 DMA engine The DMA engine handles data transfer between SDHC and system memory. Following are the features of this unit: • Supports SDMA, ADMA2, and ADMA3 modes based on the configuration. •...
Page 356: Initialization Sequence
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) To use the 32-bit block count register when HOST_CTRL2_R.HOST_VER4_EN = 1, it must be programmed with a non-zero value and the value of the 16-bit block count register BLOCK_COUNT_R must be zero. See the respective specifications documents listed in “Block diagram”...
Page 357: Enabling Sdhc
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.10.1 Enabling SDHC Ensure clk_sys is configured to be greater than or equal to clk_card and is running. Then, follow the sequence in Figure 26-6 to enable the block. The internal clock can also be enabled later during clock setup. It must be enabled to detect card insertion or removal through general interrupts when SDHC is not in standby mode.
Page 358 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) START GP_OUT_R.CARD_DETECT_EN = 1 IS PSTATE_REG.CARD_ STABLE = 1? Card is not present IS PSTATE_REG.CARD_ INSERTED = 1? Card is present Figure 26-7. Card status check sequence START GP_OUT_R.CARD_DETECT_EN = 1 Enable interrupt for Card Detect WUP_CTRL_R = 0...
Page 359: Sdhc Initialization
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.10.3 SDHC initialization To initialize SDHC, configure the basic settings as shown in Figure 26-9. This step can also be executed immediately after enabling SDHC. START Enable power to the card GP_OUT_R.CARD_IF_PWR_EN_OE = 1 PWR_CTRL_R.SD_BUS_PWR_VDD1 = 1 GP_OUT_R.IO_VOLT_SEL_OE = 1...
Page 360: Clock Setup
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.10.4 Clock setup Enable the internal clock followed by the card clock (SD clock) by following the sequence shown in Figure 26-10. The SD clock frequency must be 100 kHz to 400 kHz during the card initialization. See “Card clock (SDCLK) configuration”...
Page 361: Error Detection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Secure digital host controller (SDHC) 26.11 Error detection SDHC can detect different types of errors in SD and eMMC transactions. Error is detected in either the command or data portion of the transaction. When an error is detected, the ERR_INTERRUPT bit in the NORMAL_INT_STAT_R register is set.
Page 362: Serial Communications Block (Scb)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Serial Communications Block (SCB) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 363: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.2 Architecture The operation modes supported by SCB are described in the following sections. 27.2.1 Buffer modes Each SCB has 256 bytes of dedicated RAM for transmit and receive operation. This RAM can be configured in three different modes (FIFO, EZ, or CMD_RESP).
Page 364: Clocking Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.2.2 Clocking modes The SCB can be clocked either by an internal clock provided by the peripheral clock dividers (referred to as clk_scb in this document), or it can be clocked by the external master. •...
Page 365: Serial Peripheral Interface (Spi)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.3 Serial peripheral interface (SPI) The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master initiates the data transfer. The SCB supports single-master-multiple-slaves topology for SPI. Multiple slaves are supported with individual slave select lines.
Page 366: General Description
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.3.2 General description Figure 27-1 illustrates an example of SPI master with four slaves. SCLK MOSI MISO Slave 1 Master Slave Select (SS) 1 Slave 2 Slave Select (SS) 2 Slave 3 Slave Select (SS) 3 Slave 4...
Page 367: Spi Modes Of Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) By default, the SPI interface supports a data frame size of eight bits (1 byte). The data frame size can be configured to any value in the range 4 to 16 bits. The serial data can be transmitted either most significant bit (MSb) first or least significant bit (LSb) first.
Page 368 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) CPOL = 0 CPHA = 0 SCLK MISO / MOSI CPOL = 0 CPHA = 1 SCLK MISO / MOSI CPOL = 1 CPHA = 0 SCLK MISO / MOSI CPOL = 1 CPHA = 1...
Page 369: Texas Instruments Spi
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) CPHA = 0, CPOL = 0 Oversampling = 5 (1 SCLK period contains 6 clk_scb periods) clk_scb SCLK ¼ SCLK ¾ SCLK CPHA = 1, CPOL = 0 Oversampling = 5 (1 SCLK period contains 6 clk_scb periods) clk_scb SCLK ¼...
Page 370 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) single data transfer CPOL=0, CPHA=1 SCLK MOSI MISO two successive data transfers CPOL=0, CPHA=1 SCLK LSb MSb MOSI MISO LSb MSb Figure 27-5. SPI TI data transfer example Figure 27-6 illustrates a single 8-bit data transfer and two successive 8-bit data transfers.
Page 371: National Semiconductors Spi
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Configuring SCB for SPI TI mode To configure the SCB for SPI TI mode, set various register bits in the following order: 1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register. 2.
Page 372: Spi Buffer Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Configuring SCB for SPI NS mode To configure the SCB for SPI NS mode, set various register bits in the following order: 1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register. 2.
Page 373: Ezspi Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Note: Before going into deep sleep the wakeup interrupt should be cleared. See the “SPI interrupts” page 418 for more details. Deep Sleep to Active transition EC_AM = 1, EC_OP = 0, FIFO mode. When the SPI Slave Select line is asserted the device will be awoken by an interrupt.
Page 374 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Memory Array Write A write to a memory array index starts with a command byte (0x01) on the MOSI line indicating the master’s intent to write to the memory array. The slave then drives a reply byte on the MISO line to indicate that the command was registered (0xFE) or not (0xFF).
Page 375 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Command 0x00 : Write EZ address SCLK Command 0x00 EZ Address MOSI MISO EZ address (8 bits) EZ address Command 0x01 : Write DATA SCLK Write DATA Command 0x01 MOSI MISO Write...
Page 376: Command-Response Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) For more information on these registers, see the registers reference manual. Active to Deep Sleep transition Before going to deep sleep ensure the master is not currently transmitting to the slave. This can be done by checking the BUS_BUSY bit in the SPI_STATUS register.
Page 377 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) the slave’s base read address. Transmitted data elements are read from the current address memory location. After each read data element is transferred, the current read address is incremented. During the reception of the first byte, the slave (MISO) transmits either 0x62 (ready) or a value different from 0x62 (busy).
Page 378: Clocking And Oversampling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Configuring SCB for CMD_RESP mode By default, the SCB is configured for non-CMD_RESP mode of operation. To configure the SCB for CMD_RESP mode, set the register bits in the following order: 1.
Page 379 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) • EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘1’. Use this mode when both Active and Deep Sleep functionality are required. When the slave is selected, INTR_SPI_EC.WAKE_UP is set to ‘1’. The associated Deep Sleep functionality interrupt brings the system into Active power mode.
Page 380: Using Spi Master To Clock Slave
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.3.5.2 Using SPI master to clock slave In a normal SPI Master mode transmission, the SCLK is generated only when the SCB is enabled and data is being transmitted. This can be changed to always generate a clock on the SCLK line while the SCB is enabled. This is used when the slave uses the SCLK for functional operations other than just the SPI functionality.
Page 381: Enabling And Initializing Spi
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) spi_ select CPOL : 0 , CPHA : 0 spi_clk spi_ mosi spi_ miso late MISO sample normal MISO sample Figure 27-11. MISO sampling timing This changes the equation to: ...
Page 382: I/O Pad Connection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) operation mode (from Motorola mode to TI mode) or to go from externally clocked to internally clocked operation. The change takes effect only after the block is re-enabled. Note: Re-enabling the block causes re- initialization and the associated state is lost (for example, FIFO content).
Page 383: Spi Slave
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.3.7.2 SPI slave Figure 27-13 Table 27-5 list the use of I/O pads for SPI slave. spi_clk_out_en spi_ctl don t care spi_clk_out spi_clk spi_clk_in spi_clk_in Input only spi_select_out_en spi_ctl don t care spi_select_out spi_select...
Page 384: Glitch Avoidance At System Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.3.7.3 Glitch avoidance at system reset The SPI outputs are in high-impedance digital state when the device is coming out of system reset. This can cause glitches on the outputs. This is important if you are concerned with SPI master SS0 – SS3 or SCLK output pins activity at either device startup or when coming out of Hibernate mode.
Page 385: Uart
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Table 27-6. SPI Registers (continued) Register name Operation SCB_TX_FIFO_STATUS Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides whether the transmitter FIFO holds the valid data.
Page 386: General Description
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.4.2 General description Figure 27-14 illustrates a standard UART TX and RX. UART UART Figure 27-14. UART example A typical UART transfer consists of a start bit followed by multiple data bits, optionally followed by a parity bit and finally completed by one or more stop bits.
Page 387 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) Tx / Rx STOP START START DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA IDLE LEGEND: Tx / Rx : Transmit or Receive line Figure 27-15.
Page 388 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Parity This functionality adds a parity bit to the data frame and is used to identify single-bit data frame errors. The parity bit is always directly after the data frame bits. The transmitter calculates the parity bit (when UART_TX_CTRL.PARITY_ENABLED is 1) from the data frame bits, such that data frame bits and parity bit have an even (UART_TX_CTRL.PARITY is 0) or odd (UART_TX_CTRL.PARITY is 1) parity.
Page 389 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) uart_rx IDLE/STOP START START Active Active power mode A -> DS Deep Sleep DS -> A UART not operational UART RX synchronizes CPU enables Rx functionality UART Rx Setup IOSS/GPIO IOSS/GPIO wake up interrupt synchronizes Figure 27-19.
Page 390 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Flow control The standard UART mode supports flow control. Modem flow control controls the pace at which the transmitter transfers data to the receiver. Modem flow control is enabled through the UART_FLOW_CTRL.CTS_ENABLED register field.
Page 391: Uart Local Interconnect Network (Lin) Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) The main properties of UART_MP mode are: • Single master with multiple slave concept (multi-drop network). • Each slave is identified by a unique address. • Using 9-bit data field, with the ninth bit as address/data flag (MP bit). When set high, it indicates an address byte;...
Page 392 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) LIN Master 1 LIN Slave 1 LIN Slave 2 UART LIN UART LIN UART LIN LIN Transceiver LIN Transceiver LIN Transceiver LIN BUS Figure 27-24. UART_LIN and LIN transceiver LIN protocol defines two tasks: •...
Page 393 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) In LIN protocol communication, the least significant bit (LSb) of the data is sent first and the most significant bit (MSb) last. The start bit is encoded as zero and the stop bit is encoded as one. The following sections describe all the byte fields in the LIN frame.
Page 394 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) • Enhanced checksum: the checksum calculated over all the data bytes along with the protected identifier (used in LIN 2.x slaves). LIN frame types The type of frame refers to the conditions that need to be valid to transmit the frame. According to the LIN specification, there are five different types of LIN frames.
Page 395: Smartcard (Iso 7816)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) This behavior is application specific. The LIN slave nodes automatically enter Sleep mode if the LIN bus inactivity is more than four seconds. Wake-up can be initiated by any node connected to the LIN bus – either LIN master or any of the LIN slaves by forcing the bus to be dominant for 250 µs to 5 ms.
Page 396: Infrared Data Association (Irda)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Configuring SCB as UART SmartCard interface To configure the SCB as a UART SmartCard interface, set various register bits in the following order; note that ModusToolbox™ does all this automatically with the help of GUIs. For more information on these registers, see registers reference manual.
Page 397: Clocking And Oversampling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.4.4 Clocking and oversampling The UART protocol is implemented using clk_scb as an oversampled multiple of the baud rate. For example, to implement a 100-kHz UART, clk_scb could be set to 1 MHz and the oversample factor set to ‘10’. The oversampling is set using the SCB_CTRL.OVS register field.
Page 398: I/O Pad Connection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.4.6 I/O pad connection 27.4.6.1 Standard UART mode Figure 27-32 Table 27-7 list the use of the I/O pads for the Standard UART mode. uart_tx_ctl uart_tx_out_en uart_tx_out uart_tx_out uart_tx uart_tx_in uart_tx_in Normal...
Page 399: Lin Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Table 27-8. SmartCard mode I/O pad connections I/O pads Drive mode On-chip I/O Usage signals uart_tx Open drain uart_tx_in Used to receive a data element. with pull-up Receive a negative acknowledge-ment of a transmitted data element uart_tx_out_en Transmit a data element.
Page 400: Irda Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.4.6.4 IrDA mode Figure 27-35 Table 27-10 list the use of the I/O pads for IrDA mode. uart_tx_out_en uart_tx_ctl Normal uart_tx_out uart_tx_out output mode IrDA uart_tx uart_tx_in uart_tx_in transducer module uart_rx_out_en uart_rx_ctl...
Page 401: Inter Integrated Circuit (I2C)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5 Inter integrated circuit (I This section explains the I C implementation in the PSoC™ 6 MCU. For more information on the I C protocol specification, see the I C-bus specification available on the website.
Page 402: External Electrical Connections
) are primarily determined by the supply voltage, bus speed, and bus capacitance. For detailed information on how to calculate the optimum pull-up resistor value for your design Infineon recommends using the UM10204 I C-bus specification and user manual Rev. 6, available from the NXP website at www.nxp.com.
Page 403: Terms And Definitions
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) • = Total input leakage current of all devices on the bus The supply voltage (V ) limits the minimum pull-up resistor value due to bus devices maximum low output voltage (V ) specifications.
Page 404: Bus Arbitration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.4.2 Bus arbitration The I C protocol is a multi-master, multi-slave interface. Bus arbitration is implemented on master devices by monitoring the SDA line. Bus collisions are detected when the master observes an SDA line value that is not the same as the value it is driving on the SDA line.
Page 405: Write Transfer
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.5.1 Write transfer • A typical write transfer begins with the master generating a START condition on the I C bus. The master then writes a 7-bit I C slave address and a write indicator (‘0’) after the START condition. The addressed slave transmits an acknowledgment byte by pulling the data line low during the ninth bit time.
Page 406: I2C Buffer Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) • If the slave acknowledges the address, it starts transmitting data after the acknowledgment signal. The master transmits an acknowledgment to confirm the receipt of each data byte sent by the slave. Upon receipt of this acknowledgment, the addressed slave may transmit another data byte.
Page 407: Ezi2C Mode
27.5.6.2 EZI2C mode The Easy I C (EZI2C) protocol is a unique communication scheme built on top of the I C protocol by Infineon. It uses a meta protocol around the standard I C protocol to communicate to an I C slave using indexed memory transfers.
Page 408 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) EZI2C distinguishes three operation phases: • Address phase: The master transmits an 8-bit address to the slave. This address is used as the slave base and current address. • Write phase: The master writes 8-bit data element(s) to the slave’s memory buffer.
Page 409: Command-Response Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.6.3 Command-response mode This mode has a single memory buffer, a base read address, a current read address, a base write address, and a current write address that are used to index the memory buffer. The base addresses are provided by the CPU. The current addresses are used by the slave to index the memory buffer for sequential accesses of the memory buffer.
Page 410: Clocking And Oversampling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.7 Clocking and oversampling The SCB I C supports both internally and externally clocked operation modes. Two bitfields (EC_AM_MODE and EC_OP MODE) in the SCB_CTRL register determine the SCB clock mode. EC_AM_MODE indicates whether I address matching is internally (0) or externally (1) clocked.
Page 411: Glitch Filtering
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) • If the BLOCK bitfield of SCB_CTRL is ‘0’: An internal logic access to the memory buffer is not blocked, but fails when it conflicts with an external interface logic access. A read access returns the value 0xFFFF:FFFF and a write access is ignored.
Page 412: Oversampling And Bit Rate
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) When operating in EC_OP_MODE = 1, the 100-kHz, 400-kHz, and 1000-kHz modes require the following settings for AF_out: AF_in AF_out DF_in 100-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 3 400-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 3 1000-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 1 27.5.7.2 Oversampling and bit rate Internally-clocked master...
Page 413 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) SCL_out SCL_bus SCL_in Figure 27-43. I C SCL turnaround path If the above three delays combined are greater than one clk_scb cycle, then the high phase of the SCL will be extended.
Page 414: Enabling And Initializing The I2C
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.8 Enabling and initializing the I The following section describes the method to configure the I C block for standard (non-EZ) mode and EZI2C mode. 27.5.8.1 Configuring for I C FIFO mode The I C interface must be programmed in the following order.
Page 415: I/O Pad Connections
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.9 I/O pad connections i2c_ic_block_ec i2c_ctl i2c_ic_scl_out Open drain i2c_ic_sda_out (pull-up) i2c_scl Filter i2c_scl_in i2c_scl_in i2c_sda_in Filter i2c_ec_ctl i2c_ec_scl_out i2c_ec_sda_out i2c_sda Filter i2c_sda_in i2c_scl_in Open drain i2c_sda_in (pull-up) Figure 27-44. I C I/O pad connections Table 27-19.
Page 416: I2C Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.5.10 C Registers The I C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed Table 27-20. Table 27-20. I C Registers Register Function SCB_CTRL...
Page 417: Scb Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.6 SCB interrupts SCB supports interrupt generation on various events. The interrupts generated by the SCB block vary depending on the mode of operation. Table 27-21. SCB interrupts Interrupt Functionality Active/Deep Registers...
Page 418: Spi Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Note: While registers corresponding to INTR_M are used here, these definitions can be used for INTR_S, INTR_TX, INTR_RX, INTR_I2C_EC, and INTR_SPI_EC. Figure 27-45 shows the physical interrupt lines. All the interrupts are OR'd together to make one interrupt source that is the OR of all six individual interrupts.
Page 419 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) – TX FIFO overflow – Firmware attempts to write to a full TX FIFO. – TX FIFO underflow – Hardware attempts to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is ‘1’.
Page 420 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Component Started Write 1 byte Write 1 more byte Write 4 more bytes Write 3 more bytes TX FIF O Empty TX FIF O Empty TX FIF O Empty TX FIF O Empty = 0 (W1C) TX FIF O Empty...
Page 421: Uart Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 0 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1...
Page 422 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) – TX NACK – UART transmitter receives a negative acknowledgment in SmartCard mode. – TX done – This happens when the UART completes transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty).
Page 423 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Component Started Write 1 byte Write 1 more byte Write 4 more bytes Write 3 more bytes TX FIF O Empty TX FIF O Empty TX FIF O Empty TX FIF O Empty = 0 (W1C) TX FIF O Empty...
Page 424 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 0 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1...
Page 425: I2C Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) 27.6.3 C interrupts C interrupts can be classified as master interrupts, slave interrupts, TX interrupts, RX interrupts, and externally clocked (EC) mode interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the section.
Page 426 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial Communications Block (SCB) – TX FIFO underflow – Hardware attempts to read from an empty TX FIFO. • C RX – RX FIFO has more entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL. –...
Page 427: Serial Memory Interface (Smif)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) Serial memory interface (SMIF) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 428 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) The XIP mode of operation maps the external memory space to a range of addresses in the PSoC™ 6 MCU’s address space. See the registers reference manual for details. When this address range is accessed, the hardware automatically generates the commands required to initiate the associated transfer from the external memory.
Page 429: Tx And Rx Fifos
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) In the MMIO AHB-Lite interface, access is supported through software writes to transmit (Tx) FIFOs and software reads from receive (Rx) FIFOs. The FIFOs are mapped on SMIF registers. This interface provides the flexibility to implement any memory device transfer.
Page 430: Tx Data Fifo
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) de-asserts the slave select); that is, it must be followed by another command. Note that the DUMMY COUNT command does not assert the slave select lines. This must be done by a Tx command preceding it. Together, the four command types can be used to construct any SPI transfer.
Page 431: Command Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) 28.2.2 Command mode If CTL.XIP_MODE is ‘0’, the SMIF is in Command mode. Software generates SPI transfers by accessing the Tx FIFOs and Rx FIFO. Software writes to the Tx FIFOs and reads from the Rx FIFO. The Tx command FIFO has formatted commands (Tx, TX_COUNT, RX_COUNT, and DUMMY_COUNT) that are described in the registers reference manual.
Page 432: Cache
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) • The SMIF is not in XIP_MODE (SMIFn_CTL.XIP_MODE is ‘0’). • The transfer request is not in a memory region. • The transfer is a write and the identified memory region does not support writes (SMIFn_DEVICEn_CTL.WR_EN is ‘0’).
Page 433: Cryptography
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) 28.2.7 Cryptography In XIP mode, a cryptography component supports on-the-fly encryption for write data and on-the-fly decryption for read data. The use of on-the-fly cryptography is determined by a device’s MMIO CTL.CRYPTO_EN field. In Command mode, the cryptography component is accessible through a register interface to support offline encryption and decryption.
Page 434: Memory Device Signal Interface
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) encrypted read data encrypted write data ciphertext CT[127:0] {CRYPTO_KEY3, AES-128 forward CRYPTO_KEY2, block cipher CRYPTO_KEY1, CRYPTO_KEY0} decrypted read data decrypted write data {CRYPTO_INPUT3, CRYPTO_INPUT2, CRYPTO_INPUT1, A[31:4], CRYPT0_INPUT0.INPUT[3:0]} Figure 28-3. XIP mode functionality 28.3 Memory device signal interface The SMIF acts as a master for SPI applications.
Page 435: Connecting Spi Memory Devices
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) In dual quad SPI mode, each memory device contributes a 4-bit nibble for each 8-bit byte. However, both memory devices are quad SPI memories with a byte interface. Therefore, the transfer size must be a multiple of 2. The XIP_ALIGNMENT_ERROR interrupt cause is set under the following conditions (in XIP mode and when ADDR_CTL.DIV2 is ‘1’): •...
Page 436 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) • Use shared data signal connections. • Use dedicated data signal connections. This reduces the load on the data lines allowing faster signal level changes, which in turn allows for a faster I/O interface. Note that dual-quad SPI mode requires dedicated data signals to enable read and/or write data transfer from and to two quad SPI devices simultaneously.
Page 437 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) Figure 28-6 illustrates memory devices 0 and 1, both of which are single SPI memories. Each device uses dedicated data signal connections. The device address regions in the PSoC™ 6 MCU address space must be non- overlapping to ensure that the activation of select[0] and select[1] are mutually exclusive.
Page 438 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) CTL.DATA_SEL[1:0] = 0 Device 0: Quad SPI spi_clk memory SMIF spi_select[0] SI/IO0 SO/IO1 WP/IO2 HOLD/IO3 spi_data[0] spi_data[1] spi_data[2] spi_data[3] Figure 28-8. Quad SPI memory device 0 Figure 28-9 illustrates memory devices 0 and 1, device 0 is a single SPI memory and device 1 is a quad SPI memory.
Page 439 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) CTL.DATA_SEL[1:0] = 0 Device 0: SPI memory spi_clk SMIF spi_select[0] spi_select[1] CTL.DATA_SEL[1:0] = 0 Device 1: Quad SPI spi_data[0] memory spi_data[1] spi_data[2] SI/IO0 spi_data[3] SO/IO1 WP/IO2 HOLD/IO3 Figure 28-10. Single SPI memory device 0 and Quad SPI memory device 1 - Shared data signal Figure 28-11 illustrates memory devices 0 and 1, both of which are quad SPI memories.
Page 440: Spi Data Transfer
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) CTL.DATA_SEL[1:0] = 0 Device 0: Octal SPI spi_clk memory SMIF spi_select[0] spi_data[0] spi_data[1] spi_data[2] spi_data[3] spi_data[4] spi_data[5] spi_data[6] spi_data[7] Figure 28-12. Octal SPI memory device 0 28.3.3 SPI data transfer SPI data transfer uses most-significant-bit (MSb) for the first data transfer.
Page 441 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) For a dual SPI device and device data signal connections to data[1:0] (DATA_SEL is “0”), Table 28-4 summarizes the transfer of byte B. Table 28-4. Dual data transfer Cycle Data transfer b7, b6 are transferred on data[1:0] and IO1, IO0.
Page 442: Example Of Setting Up Smif
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) 28.3.4 Example of setting up SMIF Devices 0 and 1 are used to implement the dual-quad SPI mode. Both devices are 1 MB / 8 Mb; the address requires 3 bytes. Device 0 has device data signal connections to data[3:0] and device 1 has device data signal connections to data[7:4].
Page 443: Triggers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) 0xEB instruction, instruction 1 bit/cycle; address, mode, data 4 bits/cycle spi_select[0] spi_select[1] spi_clk 4 dummy 24 bit address instruction (0xeb) 8-bit data mode cycles spi_data[0] spi_data[1] spi_data[2] spi_data[3] spi_data[4] spi_data[5] spi_data[6] spi_data[7]...
Page 444: Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Serial memory interface (SMIF) • The MMIO RX_DATA_FIFO_CTL.TRIGGER_LEVEL field specifies a number of FIFO entries. The tr_rx_req trigger is active when the number of used Rx data FIFO entries is greater than the specified number; that is, RX_DATA_FIFO_STATUS.USED >...
Page 445: Can Fd Controller
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller CAN FD controller This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 446: Features Not Supported
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Note: See the device datasheet to identify which device supports M_TTCAN and the total size of the related MRAM. 29.1.2 Features not supported • Asynchronous serial communication (ASC) • Interrupt of Bit Error Corrected (IR.BEC) in M_TTCAN –...
Page 447: Functional Description
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3 Functional description 29.3.1 Operation modes 29.3.1.1 Software initialization This refers to setting or resetting the initialization bit (CCCR.INIT). The CCCR.INIT bit is set • either by software or hardware reset •...
Page 448: Normal Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Message RAM initialization Each MRAM word should be reset by writing 0x00000000 before configuration of the CAN FD controller. This prevents MRAM bit errors when reading uninitialized words, and also avoids unexpected filter element configurations in MRAM.
Page 449: Transmitter Delay Compensation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller • During system startup, all nodes transmit classic CAN messages until it is verified that they can communicate in CAN FD format. If this is true, all nodes switch to CAN FD operation. •...
Page 450: Restricted Operation Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller time in the data phase). The position of the secondary sample point is rounded down to the next integer number of mtq (clk_can period). PSR.TDCV shows the actual transmitter delay compensation value. PSR.TDCV is cleared when CCCR.INIT is set and is updated at each transmission of an FD frame while DBTP.TDC is set.
Page 451: Bus Monitoring Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller The CPU can set the CAN FD controller into Restricted Operation mode by setting the Restricted Operation mode bit (CCCR.ASM). CCCR.ASM can only be set by the CPU when both CCCR.CCE and CCCR.INIT are set to ‘1‘. CCCR.ASM can be reset by the CPU at any time.
Page 452: Power Down (Sleep Mode)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller • Arbitration lost or frame transmission disturbed: Corresponding TX Buffer Transmission Occurred bit TXBTO.TOx not set Corresponding TX Buffer Cancellation Finished bit TXBCF.CFx set In successful frame transmissions, and if storage of TX events is enabled, a TX Event FIFO element is written with Event Type ET = 10 (transmission despite cancellation).
Page 453: Application Watchdog
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Internal Loop Back mode Internal Loop Back mode is entered by programming the TEST.LBCK and CCCR.MON bits to one. This mode can be used for a “Hot Selftest”, meaning the M_TTCAN can be tested without affecting a running CAN system connected to the canfd[0].ttcan_tx[0] and canfd[0].ttcan_rx[0] pins.
Page 454: Timeout Counter
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.3 Timeout counter To signal timeout conditions for RX FIFO 0, RX FIFO 1, and the TX Event FIFO, the M_TTCAN supplies a 16-bit Timeout Counter. It operates as down-counter and uses the same prescaler controlled by TSCC.TCP as the timestamp Counter.
Page 455 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Depending on the configuration of the filter element (SFEC/EFEC) a match triggers one of the following actions: • Store received frame in FIFO 0 or FIFO 1 • Store received frame in RX buffer •...
Page 456 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Standard Message ID filtering Figure 29-5 shows the flow for standard Message ID (11-bit Identifier) filtering. The Standard Message ID Filter element is described in “Standard Message ID filter element” on page 478.
Page 457 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Extended Message ID filtering Figure 29-6 shows the flow for extended Message ID (29-bit Identifier) filtering. The Extended Message ID Filter element is described in “Extended Message ID filter element” on page 480.
Page 458: Rx Fifos
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.4.2 RX FIFOs RX FIFO 0 and RX FIFO 1 can be configured to hold up to 64 elements each. The two RX FIFOs are configured via the RXF0C and RXF1C registers. Received messages that pass acceptance filtering are transferred to the RX FIFO as configured by the matching filter element.
Page 459 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller If a message is received while the corresponding RX FIFO is full, this message is discarded and the message lost condition is signaled by RXFnS.RFnL = 1. In addition, the interrupt flag IR.RFnL is set. RX FIFO Overwrite mode The RX FIFO overwrite mode is configured by RXFnC.FnOM = 1.
Page 460: Dedicated Rx Buffers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller • Reduced power • Enables DMA access to FIFO This logic is enabled when RXFTOP_CTL.FnTPE is set. Setting this bit enables the logic to set the FIFO top address (FnTA) and internal message word counter. Receive FIFO in the top status register (RXFTOPn_STAT) shows the respective FIFO top address and RXFTOPn_DATA provides the data located at the top address.
Page 461: Debug On Can Support
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.4.4 Debug on CAN support Debug messages are stored into RX buffers; three consecutive RX buffers (for example, #61, #62, and #63) should be used to store debug messages A, B, and C. The format is the same for RX buffer and RX FIFO elements. To ﬁlter debug messages Standard/Extended Filter Elements with SFEC/EFEC = 111 should be set up.
Page 462: Tx Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller HW reset or Init state DMS = "00" DMS = "11" DMS = "01" DMS = "10" T0: reset DMA request, enable reception of debug messages A, B, and C T1: reception of debug message A T2: reception of debug message A T3: reception of debug message C...
Page 463: Transmit Pause
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.5.1 Transmit pause The transmit pause feature is intended for use in CAN systems where the CAN message identifiers are (permanently) assigned to specific values and cannot be changed easily. These message identifiers may have a higher CAN arbitration priority than other defined messages, while in a specific application their relative arbitration priority should be inverse.
Page 464: Tx Fifo
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.5.3 TX FIFO TX FIFO operation is configured by programming TXBC.TFQM to '0'. Messages stored in the TX FIFO are transmitted starting with the message referenced by the Get Index TXFQS.TFGI. After each transmission, the Get Index is incremented cyclically until the TX FIFO is empty.
Page 465: Mixed Dedicated Tx Buffers/Tx Fifo
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.5.5 Mixed dedicated TX buffers/TX FIFO In this case, the TX Buffers section in the MRAM is subdivided into a set of dedicated TX buffers and a TX FIFO. The number of dedicated TX buffers is configured by TXBC.NDTB.
Page 466: Transmit Cancellation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.5.7 Transmit cancellation The M_TTCAN supports transmit cancellation. This feature is especially intended for gateway applications and AUTOSAR-based applications. To cancel a requested transmission from a dedicated TX buffer or a TX Queue buffer the host must write a '1' to the corresponding bit position (number of TX buffers) of the TXBCR register.
Page 467: Fifo Acknowledge Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.3.6 FIFO acknowledge handling The Get indices of RX FIFO 0, RX FIFO 1, and the TX Event FIFO are controlled by the corresponding FIFO Acknowledge Index. When RX FIFO top pointer hardware logic is used, it updates the RX FIFO Acknowledge Index. After RXFTOPn_DATA is read, the Acknowledge Index (RXFnA.FnA) is updated automatically, which will eventually set the FIFO Get Index to the FIFO Acknowledge Index plus one and thereby updates the FIFO Fill Level.
Page 468 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller A bit time Sync_Seg Prop_Seg Phase_Seg1 Phase_Seg2 A time quantum Sampling point Figure 29-12. Bit time construction Each segment consists of a programmable number of time quanta, which is a multiple of the time quantum that is defined by clk_can and a prescaler.
Page 469: Can Bit Rates
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller These relations result in the following equations for the nominal and data bit times: Nominal Bit time = [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] × tq = [1 + (NBTP.NTSEG1[7:0] + 1) + (NBTP.NTSEG2[6:0] + 1)] × [(NBTP.NBRP[8:0] +1) × clk_can period] Data Bit time = [1 + (DBTP.DTSEG1[4:0] + 1) + (DBTP.DTSEG2[3:0] + 1)] ×...
Page 470: Message Ram
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller CAN clock 8MHz 10MHz 16MHz 20MHz 32MHz 40MHz frequency configuration data bit rate 16tqd 20tqd 32tqd 40tqd 32tqd 40tqd 8tqd 10tqd 16tqd 20tqd 16tqd 20tqd 500Kbps 8tqd 10tqd 8tqd 10tqd 8tqd 10tqd 16tqd...
Page 471: Rx Buffer And Fifo Element
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Address SIDFC.FLSSA 11-bit Filter 0-128 elements / 0-128 words XIDFC.FLESA 29-bit Filter 0-64 elements / 0-128 words RXF0C.F0SA Rx FIFO 0 0-64 elements / 0-1152 words RXF1C.F1SA max. 4480 words Rx FIFO 1 0-64 elements / 0-1152 words RXBC.RBSA...
Page 472 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 16 15 ID[28:0] FIDX[6:0] DLC[3:0] RXTS[15:0] DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0] DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] DBm[7:0] DBm-1[7:0] DBm-2[7:0] DBm-3[7:0] Figure 29-16. RX buffer and FIFO R0 [bit31] ESI: Error State Indicator Description Transmitting node is error active.
Page 473 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Acceptance of non-matching frames may be enabled via GFC.ANFS[1:0] (Accept Non-matching Frames Standard) and GFC.ANFE[1:0] (Accept Non-matching Frames Extended). Description Received frame matching filter index FIDX. Received frame did not match any RX filter element. R1 [bit30:24] FIDX[6:0]: Filter Index FIDX[6:0] Description...
Page 474: Tx Buffer Element
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller … … … Rn [bit31:24] DBm[7:0]: Data Byte m Rn [bit23:16] DBm-1[7:0]: Data Byte m-1 Rn [bit15:8] DBm-2[7:0]: Data Byte m-2 Rn [bit7:0] DBm-3[7:0]: Data Byte m-3 Note: • Depending on the configuration of the element size (defined by RX buffer/FIFO Element Size Configuration (RXESC)), Rn will vary from n = 3 to 17.
Page 475 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Note: The ESI bit of the transmit buffer is ORed with the error passive flag to decide the value of the ESI bit in the transmitted FD frame. As required by the CAN FD protocol specification, an error active node may optionally transmit the ESI bit recessive, but an error passive node will always transmit the ESI bit recessive.
Page 476: Tx Event Fifo Element
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller T1 [bit19:16] DLC[3:0]: Data Length Code DLC[3:0] Description Classic CAN + CAN FD: transmit frame has 0-8 data bytes. 9-15 Classic CAN: transmit frame has 8 data bytes. CAN FD: transmit frame has 12/16/20/24/32/48/64 data bytes. T1 [bit15:0] Reserved: Reserved Bits When writing, always write ‘0’.
Page 477 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller E0 [bit31] ESI: Error State Indicator Description Transmitting node is error active. Transmitting node is error passive. E0 [bit30] XTD: Extended Identifier Description 11-bit standard identifier. 29-bit extended identifier. E0 [bit29] RTR: Remote Transmission Request Description Data frame transmitted.
Page 478: Standard Message Id Filter Element
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller E1 [bit19:16] DLC[3:0]: Data Length Code DLC[3:0] Description Classic CAN + CAN FD: frame with 0-8 data bytes transmitted. 9-15 Classic CAN: frame with 8 data bytes transmitted. CAN FD: frame with 12/16/20/24/32/48/64 data bytes transmitted. Table 29-1 for details.
Page 479 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller If SFEC[2:0] = 100, 101, or 110 a match sets interrupt flag IR.HPM (High Priority Message) and, if enabled, an interrupt is generated. In this case register HPMS (High Priority Message Status) is updated with the status of the priority match.
Page 480: Extended Message Id Filter Element
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.4.6 Extended Message ID filter element An Extended Message ID Filter Element consists of two 32-bit words, and can be configured as a range filter, dual filter, classic bit mask filter, or filter for a single dedicated ID, for messages with 29-bit extended IDs. Up to 64 filter elements can be configured for 29-bit extended IDs.
Page 481 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller F1 [bit31:30] EFT[1:0]: Extended Filter Type EFT[1:0] Description Range filter from EFID1[28:0] to EFID2[28:0] (EFID2[28:0] ≥ received ID ANDed with XIDAM ≥ EFID1[28:0]). Dual ID filter Matches when EFID1[28:0] or EFID2[28:0] is equal to received ID ANDed with XIDAM. Classic filter: EFID1[28:0] = filter, EFID2[28:0] = mask.
Page 482: Trigger Memory Element
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.4.7 Trigger memory element Up to 64 trigger memory elements can be configured. When accessing a trigger memory element, its address is the Trigger Memory Start Address TTTMC.TMSA plus the index of the trigger memory element (0…63). 16 15 ASC[ TM[15:0]...
Page 483 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller T0 Bit 4 TMEX: Time Mark Event External TMEX Description No action. Pulse at output of Trigger Time Mark with the length of one clk_can period is generated when the time mark of the trigger memory element becomes active and TTOCN.TTMIE = 1. T0 Bit 3:0 TYPE[3:0]: Trigger Type TYPE [3:0] Description...
Page 484: Mram Off
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.4.8 MRAM OFF Message RAM can be turned off to save power by setting CTL.MRAM_OFF bit. Default value of this bit is '0' and MRAM is retained in this configuration during DeepSleep power mode. The M_TTCAN channel must be powered down before setting MRAM_OFF bit.
Page 485: Level 1
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.5.1.1 Level 1 Level 1 operation is configured via TTOCF.OM = 01 and TTOCF.GEN. External clock synchronization is not available in Level 1. The information related to the reference message is stored in the first data byte as shown in Table 29-8.
Page 486: Ttcan Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.5.2 TTCAN configuration 29.5.2.1 TTCAN timing The Network Time Unit (NTU) is the unit in which all times are measured. The NTU is a constant of the whole network and is defined by the network system designer. In TTCAN Level 1 the NTU is the nominal CAN bit time. In TTCAN Level 0 and Level 2 the NTU is a fraction of the physical second.
Page 487: Message Scheduling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Table 29-11. TUR configuration examples 125000 32.5 100/12 529/17 0x1FFF8 0x1FFFE 0x1FFF8 0x1FFEA 0x1FFFE 0x1FFE0 0x1FFE0 0x19000 0x10880 TURCF.DC 0x3FFF 0x3333 0x1555 0x0A3D 0x0101 0x0001 0x0FC0 0x3000 0x0880 TTOCN.ECS schedules NC for activation by the next reference message. TTOCN.SGT schedules TTGTP.TP for activation by the next reference message.
Page 488: Trigger Memory
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Note: In case the first reference message seen by a node does not have Cycle_Count zero, this node may finish its first matrix cycle with its TX count resulting in a TX Count Underflow condition. As long as a node is in state, synchronizing its Tx_Triggers will not lead to transmissions.
Page 489 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Trigger types Tx_Ref_Trigger (TYPE = 0000) and Tx_Ref_Trigger_Gap (TYPE = 0001) cause the transmission of a reference message by a time master. A configuration error (TTOST.EL = 11, severity 3) is detected when a time slave encounters a Tx_Ref_Trigger(_Gap) in its trigger memory.
Page 490 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Restrictions for the Node's trigger list Two triggers may not be active at the same cycle time and cycle count, but triggers that are active in different basic cycles (different cycle code) may share the same time mark. Rx_Triggers and Time_Base_Triggers may not be placed inside the TX enable windows of Tx_Trigger_Single/Continuous/Arbitration, but they may be placed after Tx_Trigger_Merged.
Page 491 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Examples of trigger handling The following example shows how the trigger list is derived from a node's system matrix. Assume that node A is a first time master; a section of the system matrix shown in Table 29-12.
Page 492: Ttcan Schedule Initialization
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller When the cycle time reaches TM, the action defined by TYPE and MNR is started. There is an error in the configuration when it reaches End_of_List. At Mark6, the reference message (always TxRef) is transmitted. After transmission, the FSE returns to the beginning of the trigger list.
Page 493: Ttcan Gap Control
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Potential time master After configuration, a potential time master will start the transmission of a reference message when it reaches its Tx_Ref_Trigger (or its Tx_Ref_Trigger_Gap when in external event-synchronized time-triggered operation). It will ignore its Watch_Trigger and Watch_Trigger_Gap when it does not receive any message or transmit the reference message successfully before reaching the Watch_Triggers (the reason assumed is that all other nodes still in reset or configuration and does not acknowledge).
Page 494: Stop Watch
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller • Any potential time master will finish a gap when it reaches its Tx_Ref_Trigger_Gap, assuming that the event to synchronize to did not occur on time. None of these options can cause a basic cycle to be interrupted with a reference message. Setting TTOCN.FGP after the gap time has started will start the transmission of a reference message immediately and will thereby synchronize the message schedule.
Page 495 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Reference Message Sync_Mark Local Time Master_Ref_Mark Ref_Mark Frame Sync Mark Synchronisation Reference Ref Mark Message Valid Local Time Local_Offset Cycle Time Cycle Sync Mark Global Time Figure 29-22. Cycle time and global time synchronization The cycle time that can be read from TTCTC.CT is the difference of the node's local time and Ref_Mark, both synchronized into the host clock domain and truncated to 16 bits.
Page 496 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Reference Message actual Master_Ref_Mark previous Master_Ref_Mark Sync Mark actual Ref_Mark previous Ref_Mark Start of Basic Cycle Calibration Figure 29-23. TTCAN level 0 and level 2 drift compensation Figure 29-23 illustrates how in TTCAN Level 0 and Level 2 the receiving node compensates the drift between its own local clock and the time master's clock by comparing the length of a basic cycle in local time and in global time.
Page 497: Ttcan Error Level
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.5.6 TTCAN error level The ISO 11898-4 specifies four levels of error severity: • S0 - No error • S1 - Warning Only notification of application, reaction application-specific. • S2 - Error Notification of application.
Page 498: Ttcan Message Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Scheduling_Error_1 (S1) Sets error level TTOST.EL to ‘01’ if within one matrix cycle the difference between the maximum MSC and the minimum MSC for all trigger memory elements (of exclusive time windows) is larger than 2, or if one of the MSCs of an exclusive Rx_Trigger has reached 7.
Page 499: Message Transmission
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller The time mark of an Rx_Trigger should be set to a value that ensures reception and acceptance filtering for the targeted message is completed. This should consider the RAM access time and the order of the filter list. It is recommended, that filters used for Rx_Triggers are placed at the beginning of the filter list.
Page 500: Ttcan Interrupt And Error Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Transmission in exclusive time windows A transmission is started time-triggered when the cycle time reaches the time mark of a Tx_Trigger_Single or Tx_Trigger_Continous. There is no arbitration on the bus with messages from other nodes. The MSC is updated according the result of the transmission attempt.
Page 501: Level 0
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller The third segment consists of flags GTD, GTW, SWE, TTMI, and RTMI. The first two flags are controlled by global time events (Level 0 and Level 2 only) that require a reaction by the application program. With a Stop Watch Event, internal time values are captured.
Page 502: Synchronizing
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.5.9.1 Synchronizing Figure 29-24 describes the states and state transitions in TTCAN Level 0 operation. Level 0 has no In_Gap state. HW reset or Sync_off Init state S3 Synchronizing In_Schedule T0: transition condition always taking prevalence T1: Init state left, cycle time is zero T2: at least two successive reference messages observed...
Page 503: Master Slave Relation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.5.9.3 Master slave relation Figure 29-25 describes the master slave relation in TTCAN Level 0. In case of an S3 error, the M_TTCAN returns to state Master_Off. HW reset or HW reset or HW reset or Init state or...
Page 504: Setup Procedures
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6 Setup procedures This section provides example procedures for configurations of the M_TTCAN channel. 29.6.1 General program flow This is a general flow to configure the M_TTCAN module. Start Configure timestamp prescaler Write TS_CTL.PRESCALE Enable timestamp counter Write ‘1’...
Page 505: Clock Stop Request
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.2 Clock stop request To save power, the application can stop providing clock to the unused M_TTCAN channel by following these steps. Start Request Clock Stop Set CTL.STOP_REQ STATUS.STOP_ACK set? Figure 29-27.
Page 506: Mram On Operation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.4 MRAM ON operation Start MRAM Power On Clear CTL.MRAM_OFF SRAM power-up time expired? Reset Clock Stop Clear CTL.STOP_REQ Figure 29-29. Message RAM on procedure After switching MRAM ON again, software needs to allow a certain power-up time before MRAM can be used; that is, before STOP_REQ can be de-asserted.
Page 507: Procedures Specific To M_Ttcan Channel
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.5 Procedures specific to M_TTCAN channel This section describes sample procedure for the M_TTCAN channel. Figure 29-30 shows the general program flow. Start Configure DMA Setup for RX FIFO Enable FIFOx Top Pointers Write ‘1’...
Page 508: Can Bus Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.5.1 CAN bus configuration Start Write to Data Bit Timing and Prescaler Register (DBTP) ・Transmitter Delay Compensation (TDC) ・Data Bit Rate Prescaler (DBRP[4:0]) ・Data Bit Rate Bit Time (DTSEG1[4:0], DTSEG2[3:0], DSJW[3:0]) Write to Test Register (TEST) ・Control of Transmit Pin (TX[1:0]) ・Loop Back Mode (LBCK)
Page 509 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Write to Global Filter Configuration (GFC) ・Accept Non-matching Frames Standard (ANFS[1:0]) ・Accept Non-matching Frames Extended (ANFE[1:0]) ・Reject Remote Frames Standard (RRFS) ・Reject Remote Frames Extended (RRFE) Write to Standard ID Filter Configuration (SIDFC) ・List Size Standard(LSS[7:0]) ・Filter List Standard Start Address (FLSSA[15:2]) Write to Extended ID Filter Configuration (XIDFC)
Page 510 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Write to TX Buffer Configuration (TXBC) ・TX FIFO/Queue Mode(TFQM) ・Transmit FIFO/Queue Size(TFQS[5:0]) ・Number of Dedicated Transmit Buffers(NDTB[5:0]) ・TX Buffers Start Address(TBSA[15:2]) Write to TX Buffer Element Size Configuration (TXESC) ・TX Buffer Data Field Size (TBDS[2:0]) Write to TX Event FIFO Configuration (TXEFC) ・Event FIFO Watermark (EFWM[5:0])
Page 511: Interrupt Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.5.3 Interrupt configuration Start Write to TX Buffer Transmission Interrupt Enable (TXBTIE) Write ‘1’ to TXBTIE.TIEn, if transmission interrupt enabled Write to TX Buffer Cancellation Finished Interrupt Enable (TXBCIE) Write ‘1’ to TXBCIE.CFIEn, if cancellation finished interrupt enable Write to Interrupt Enable (IE) Write ‘1’...
Page 512: Transmit Frame Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.5.4 Transmit frame configuration Start TX Queue Use dedicated transmit buffers? Use TX FIFO or TX Queue? TX FIFO Control with TXFQS.TFQPI? Check the pending requests Check TX FIFO status Check the pending requests Read TXBRP Read TXFQS...
Page 513: Interrupt Handling
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.6.5.5 Interrupt handling Figure 29-39 shows a general interrupt handling flow chart. Start Read Interrupt Register (IR) Bus_Off status changed? Bus_Off status handling operation IR.BO = 1 Message RAM access failure handling MRAM access failure occurred? operation IR.MRAF = 1...
Page 514 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Clear Bus_Off status change interrupt Write ‘1’ to IR.BO Check Bus_Off status Read PSR.BO Status in Bus_Off PSR.BO = 1? Start Bus_Off recovery Write ‘0’ to CCCR.INIT CCCR.INIT = 0? Figure 29-40.
Page 515 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Clear TX Event FIFO-related interrupt Write ‘1’ to IR.TEFL, TEFF, TEFW, TEFN Read Event FIFO Start Address SA = TXEFC.EFSA[15:2] Calculate access pointer (AP) AP = SA + {TXEFS.EFGI[4:0] × 2} Read Transmission Event Information Event info (En) = Message RAM (AP) Event info (En+1) = Message RAM (AP+1)
Page 516 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Clear interrupt of message stored to dedicated RX buffer Write ‘1’ to IR.DRX Check the set element in dedicated RX buffer Read NDAT1 and NDAT2 Read RX buffers Start Address SA = RXBC.RBSA[15:2] Calculate access pointer (AP) AP = SA + {element ×...
Page 517 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Start Clear interrupt of high-priority message received Write ‘1’ to IR.HPM Check high-priority message status Read HPMS Message stored? HPMS.MSI[1] = 1 Message stored to FIFO0? HPMS.MSI[0] = 0 Read RX FIFO 0 Start Address Read RX FIFO 1 Start Address SA=RXF0C.F0SA[15:2] SA=RXF1C.F1SA[15:2]...
Page 518: Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller 29.7 Registers Table 29-15. Register list Register Name Description CANFD_CH_CREL Core Release Register Displays the revision of the CAN FD controller. CANFD_CH_ENDN Endian Register Checks the endianness of the CAN FD controller when accessed by the CPU.
Page 519 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Table 29-15. Register list (continued) Register Name Description CANFD_CH_XIDAM Extended ID AND Mask Defines the valid bits of a 29-bit ID for acceptance filtering. CANFD_CH_HPMS High Priority Message This register is updated every time a Message ID Status filter element configured to generate a priority event matches.
Page 520 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Table 29-15. Register list (continued) Register Name Description CANFD_CH_TXBCIE TX Buffer Cancellation The settings in this register determine which TX Finished Interrupt Enable buffer will assert an interrupt upon completion of a transmission cancellation request.
Page 521 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAN FD controller Table 29-15. Register list (continued) Register Name Description CANFD_CH_TTCSM TT Cycle Sync Mark Read-only register that shows cycle sync mark in terms of cycle time. CANFD_CH_RXFTOP_CTL Receive FIFO Top control Enables Receive FIFO Top Control logic for both FIFOs.
Page 522: Timer, Counter, And Pwm (Tcpwm)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Timer, Counter, and PWM (TCPWM) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 523: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.2 Architecture Co unter i T rigger inp uts Event Configuration 16-b it or 32-b it co unter G eneratio n registers p w m , cou nter_en interrup t und erflow , p w m _n...
Page 524: Clocking
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.2.2 Clocking Each TCPWM counter can have its own clock source and the only source for the clock is from the configurable peripheral clock dividers generated by the clocking system; see the “Clocking system”...
Page 525 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) • Stop/kill • Count • Capture/swap When starting a TCPWM for the first time it is recommended that a reload is used, because a reload will generate an overflow or underflow on startup. If start is used, an overflow or underflow will not be generated on startup. The TCPWM_CMD_RELOAD, TCPWM_CMD_STOP, TCPWM_CMD_START, and TCPWM_CMD_CAPTURE registers can be used to trigger the reload, stop, start, and capture respectively from software.
Page 526: Trigger Outputs
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = CAPTURE UP_DOWN_MODE = COUNT_UP Even number of capture Odd number of capture CAPTURE_EDGE = BOTH_EDGES events => single capture events => no capture reload capture CC_BUFF PERIOD = 4 Underflow (UN) Overflow (OV)
Page 527: Interrupts
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.2.5 Interrupts The TCPWM block provides a dedicated interrupt output for each counter. This interrupt can be generated for a terminal count (TC) or CC event. A TC is the logical OR of the OV and UN events. Four registers are used to handle interrupts in this block, as shown in Table 30-1.
Page 528: Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.2.7 Power modes The TCPWM block works in Active and Sleep modes. The TCPWM block is powered from V . The configuration registers and other logic are powered in Deep Sleep mode to keep the states of configuration registers. See Table 30-3 for details.
Page 529: Timer Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-5. Counting mode configuration Counting modes UP_DOWN_M Description ODE[17:16] UP Counting Mode Increments the counter until the period value is reached. A Terminal Count (TC) and Overflow (OV) condition is generated when the counter changes from the period value.
Page 530 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-6. Timer mode trigger input description (continued) Trigger inputs Usage Count Count event increments/decrements the counter. Capture Not used. Incrementing and decrementing the counter is controlled by the count event and the counter clock clk_counter. Typical operation will use a constant ‘1’...
Page 531 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-10. Timer mode PWM outputs PWM outputs Description Not used. pwm_n Not used. Timer Interrupt interrupt generation Reload PERIOD Start cc_match tr_cc_match Stop Trigger underflow tr_underflow Count generation overflow tr_overflow...
Page 532 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Figure 30-8 illustrates a timer in “one-shot” operation mode. Note that the counter is stopped on a tc event. MODE = TIMER UP_DOWN_MODE = COUNT_UP ONE_SHOT = 1 reload PERIOD = 4 CC = 2...
Page 533 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Figure 30-11 illustrates a timer that uses both CC and CC_BUFF registers. Note that CC and CC_BUFF are exchanged on a cc_match event. MODE = TIMER UP_DOWN_MODE = COUNT_UP AUTO_RELOAD_CC = 1 CC_BUFF reload...
Page 534 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = TIMER UP_DOWN_MODE = COUNT_UPDN1 COUNTER starts with 1 period is 2*PERIOD reload PERIOD = 4 CC = 2 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) no TC event CC event on leaving the COUNTER value...
Page 535: Configuring Counter For Timer Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = TIMER UP_DOWN_MODE = COUNT_UPDN2 COUNTER starts with 1 period is 2*PERIOD reload PERIOD = 4 CC = 2 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) no TC event CC event on leaving the COUNTER value...
Page 536: Capture Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.3.2 Capture mode The capture functionality increments and decrements a counter between 0 and PERIOD. When the capture event is activated the counter value COUNTER is copied to CC (and CC is copied to CC_BUFF). The capture functionality can be used to measure the width of a pulse (connected as one of the input triggers and used as capture event).
Page 537 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-14. Capture mode interrupt outputs Interrupt outputs Description Specified by UP_DOWN_MODE: • COUNT_UP: tc event is the same as the overflow event. • COUNT_DOWN: tc event is the same as the underflow event. •...
Page 538: Configuring Counter For Capture Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = CAPTURE UP_DOWN_MODE = COUNT_UP CAPTURE_EDGE = RISING_EDGE reload capture CC_BUFF PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Figure 30-17. Capture in up counting mode When multiple capture events are detected before the next “active count”...
Page 539: Quadrature Decoder Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 8. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (reload, start, stop, capture, and count). 9. If required, set the interrupt upon TC or CC condition. 10.
Page 540 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-19. Quadrature mode interrupt outputs Interrupt outputs Description cc_match (CC) Counter value COUNTER equals 0 or 0xFFFF or 0xFFFFFFFF (32-bit mode) or a reload/index event. Reload/index event. Table 30-20.
Page 541 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Note that a counter increment/decrement can coincide with a reload/index/tc event or with a situation cc_match event. Under these circumstances, the counter value set to either 0x8000+1 or 0x80000000+1 (increment) or 0x8000–1 or 0x80000000–1 (decrement).
Page 542 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Quadrature decoding counter cycle decrement behavior, no coinciding underflow with decr1 event underflow without decr1 event reload and decrement events Reload / Index incr1 decr1 COUNTER 0x8000 0x7FFFF 0x7ffe 0x7ffd 0x0001...
Page 543: Configuring Counter For Quadrature Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.3.3.1 Configuring counter for Quadrature mode The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows. 1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register. 2.
Page 544 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-22. PWM mode supported features Supported features Description Clock pre-scaling Pre-scales the counter clock “clk_counter”. One-shot Counter is stopped by hardware, after a single period of the counter: •...
Page 545 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-24. PWM mode interrupt output description Interrupt outputs Description Specified by UP_DOWN_MODE: • COUNT_UP: tc event is the same as the overflow event. • COUNT_DOWN: tc event is the same as the underflow event. •...
Page 546 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) pwm polarity underflow Dead time kill period pwm_dt_input overflow generation insertion cc_match pwm_n pwm_n polarity only supported in TCPWM_CNT_TR_CTRL2 PWM_DT mode Figure 30-24. PWM output generation PWM polarity and PWM_n polarity as seen in Figure 30-24, allow the PWM outputs to be inverted.
Page 547 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_UP reload PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Left aligned PWM CC = pulse width OVERFLOW_MODE = SET CC_MATCH_MODE = CLEAR Right aligned PWM CC = (PERIOD+1) –...
Page 548 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_DOWN reload -1 / 0xFFFF PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Right aligned PWM CC = pulse width - 1 UNDERFLOW_MODE = CLEAR CC_MATCH_MODE = SET Left aligned PWM...
Page 549 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Note: • The actual counter value COUNTER from before the reload event is NOT used. Instead the counter value before the reload event is considered to be 0. As a result, when the first CC value at the reload event is 0, a cc_match event is generated.
Page 550 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Right aligned PWM PWM_STOP_ON_KILL = 1 pwm and pwm_n set to programmed kill event stops counter STOP_EDGE = RISING_EDGE polarity pwm polarity = 0, pwm_n polarity = 0 cc_match pwm_dt_input kill...
Page 551 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_UPDN1 SW update SW update CC_BUFF PERIOD_BUFF reload PERIOD Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) upcounting and CC = 0 => cc_matchŏ...
Page 552: Asymmetric Pwm
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Right aligned PWM PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 0 STOP_EDGE = NO_EDGE_DET pwm polarity = 0, pwm_n polarity = 0 cc_match pwm_dt_input kill pwm_n Figure 30-35. PWM outputs when killed 30.3.4.1 Asymmetric PWM This PWM mode supports the generation of an asymmetric PWM.
Page 553 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_UPDN2 CC_BUFF reload PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Asymmetric PWM CC = PERIOD – pulse width/2 UNDERFLOW_MODE = CLEAR OVERFLOW_MODE = SET CC_MATCH_MODE = INVERT...
Page 554: Configuring Counter For Pwm Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.3.4.2 Configuring counter for PWM mode The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows. 1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register. 2.
Page 555 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Figure 30-39 illustrates dead time insertion for different dead times and different output signal polarity settings. pwm_dt_input MODE = PWM_DT dead time = 0 pwm polarity = 0 pwm_n polarity = 0 pwm_n MODE = PWM_DT...
Page 556: Configuring Counter For Pwm With Dead Time Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.3.5.1 Configuring counter for PWM with Dead Time mode The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows: 1.
Page 557 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Note: Event detection is on the peripheral clock, clk_peri. Table 30-27. PWM_PR supported features Supported features Description Clock pre-scaling Pre-scales the counter clock, clk_counter. One-shot Counter is stopped by hardware, after a single period of the counter (counter value equals period value PERIOD).
Page 558 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) The PWM_PR functionality is described as follows: • The counter value COUNTER is initialized by software (to a value different from 0). • A reload or start event starts PWM_PR operation. •...
Page 559: Configuring Counter For Pseudo-Random Pwm Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM_PR COUNTER is exactly 0xe771 reload 0xFFFF PERIOD = 0xe771 CC = 0x4000 cc_match pwm_dt_input Only the lower 15 bits of the counter value are used. Figure 30-42.
Page 560: Tcpwm Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) 30.4 TCPWM registers Table 30-31. List of TCPWM registers Register Comment Features TCPWM_CTRL TCPWM control register Enables the counter block TCPWM_CTRL_CLR TCPWM control clear register Used to avoid race-conditions on read- modify-write attempt to the CTRL register TCPWM_CTRL_SET TCPWM control set register...
Page 561 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Timer, Counter, and PWM (TCPWM) Table 30-31. List of TCPWM registers (continued) Register Comment Features TCPWM_CNT_INTR_MASK Interrupt mask register Mask for interrupt request register TCPWM_CNT_INTR_MASKED Interrupt masked request register Bitwise AND of interrupt request and mask registers Reference manual 002-27293 Rev.
Page 562: Universal Serial Bus (Usb) Host
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host Universal Serial Bus (USB) host This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 563: Usb Physical Layer (Usb Phy)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 31.2.1 USB physical layer (USB PHY) The USB includes the transmitter and receiver (transceiver), which corresponds to the USB PHY. This module allows physical layer communication with the USB device through the D+, D–, and VDDUSB pins. It handles differential mode communication with the device.
Page 564: Usb Host Operations
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 31.3 USB host operations To operate the USB as a host, the following settings are required: • Enable the pull-down resistors on both D+ and D– pins. To enable the pull-down resistors, set the DP_DOWN_EN bit and DM_DOWN_EN bit of the power control register (USBLPM_POWER_CTL) to ‘1’.
Page 565: Usb Bus Reset
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host START Enable pull down resistors on D+ and D - POWER_CTL.DP_DOWN_EN=1 POWER_CTL.DM_DOWN_EN=1 Enable Host operation HOST_CTL0.HOST=1 HOST_CTL0.ENABLE=1 Enable USB Host Clock and release the reset for USB host HOST_CTL1.USTP=0 HOST_CTL1.RST=0 INTR_USBHOST.CNNIRQ=1...
Page 566: Usb Packets
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host Pin D+ 10 ms or more Pin D- URST bit of USBHOST_HOST_STATUS CSTAT bit of USBHOST_HOST_STATUS URIRQ bit of USBHOST_INTR_USBHOST CNNIRQ bit of USBHOST_INTR_USBHOST 2.5 µs or more Write ‘1’...
Page 567 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 8. Check for token packet transfer errors using the USBHOST_HOST_ERR register. Handle the errors, if any, appropriately. 9. Read the EPnDRQ (n = 1 or 2) bit of the USBHOST_INTR_HOST_EP register. A value of ‘1’ indicates that the packet transfer ended normally.
Page 568 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host START Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘1' Set DIR bit HOST_EP1_CTL and HOST_EP2_CTL to ‘1’ or ‘0’. Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘0' Specify the target address in HOST_ADDR Configure the packet size for the endpoints using the...
Page 569 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host START Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘1' Set DIR bit HOST_EP1_CTL and HOST_EP2_CTL to ‘1’ or ‘0’. Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘0' Specify the target address in HOST_ADDR Configure the packet size for the endpoints using the...
Page 570 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host An SOF is automatically sent every 1 ms while the SOFBUSY bit of the USBHOST_HOST_STATUS register is ‘1’. Figure 31-7 depicts steps to send an SOF token. START HOST_FRAME Setting HOST_EOF Setting HOST_TOKEN setting...
Page 571: Data Packet
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 31.3.4.2 Data packet Follow these steps to send or receive a data packet after sending a token packet. • Transmitting data (host to device) – Sync pattern is automatically sent. –...
Page 572: Error Status
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 31.3.6 Error status The USB host supports detection of the following types of errors: • Stuffing error If 1 is writer to six successive bits, 0 is inserted into one bit. If 1 is successively detected in seven bits, it is regarded as a Stuffing error, and the STUFF bit of the USBHOST_HOST_ERR register is set to 1.
Page 573: Interrupt Sources
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host Write data to the TKNEN bit of HTOKEN. J-ST Sync FRAME CRC5 J-ST CMPIRQ bit (HIRQ) J-ST : J State : Token FRAME : Frame Number Figure 31-10. EOP interrupt timing diagram (for SOF token) 31.3.8 Interrupt sources The USB host generates 11 interrupts to the CPU.
Page 574: Dma Transfer Function
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host • Device connection and disconnection events The CNNIRQ bit of the USBHOST_INTR_USBHOST register is set to ‘1’ when a device connection is detected. The interrupt can be enabled by setting the CNNIRQM bit of the USBHOST_INTR_USBHOST_MASK register. When a device is disconnected, an interrupt is generated if the DIRQM bitfield of USBHOST_INTR_USBHOST_MASK is set to ‘1’.
Page 575: Packet Transfer Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 31.3.9.1 Packet transfer mode The packet transfer mode transfers each packet according to the configured data size in DMA. This transfer mode can access each buffer of the endpoints. In the packet transfer mode the OUT direction transfer (host to device) involves the following sequence of steps: 1.
Page 576: Automatic Data Transfer Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 1. After the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register is set and the interrupt handling is entered, check the transfer data size. 2. Configure the DMA register setting relevant to the number of transfers and block size corresponding to the transfer data size, and then enable DMA to start the transfer.
Page 577 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 0x22 0x11 (byte 2) (byte 1) 0x33 0x44 (byte 3) (byte 4) DMA Transfer (Write) 0x66 0x55 (byte 6) (byte 5) 0x77 0x88 (byte 7) (byte 8) Write the data to the 0x99 HOST_Epn_RW1_DR by software (byte 9)
Page 578: Suspend And Resume Operations
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host Transfer all of the data by DMA Transfer the last data by software Endpoint n Buffer Endpoint n Buffer 0x22 0x22 0x11 0x11 (byte 2) (byte 2) (byte 1) (byte 1) 0x33 0x33...
Page 579: Device Disconnection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host 31.3.11 Device disconnection The device disconnection timer starts when both the D+ and D– pins are set to LOW. If both D+ and D– remain at LOW for 2.5 µs or more, the device is considered to be disconnected. This then sets the CSTAT bit of the USBHOST_HOST_STATUS register as ‘0’...
Page 580 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) host Table 31-1. USB host registers (continued) Name Description USBHOST_INTR_USBHOST Interrupt USB host register USBHOST_INTR_USBHOST_SET Interrupt USB host set register USBHOST_INTR_USBHOST_MASK Interrupt USB host mask register USBHOST_INTR_USBHOST_MASKED Interrupt USB host masked register USBHOST_INTR_HOST_EP Interrupt USB host endpoint register USBHOST_INTR_HOST_EP_SET...
Page 581: Universal Serial Bus (Usb) Device Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Universal Serial Bus (USB) device mode This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 582: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.2 Architecture Figure 32-1 illustrates the device architecture of the USB block in PSoC™ 6 MCUs. It consists of the USB Physical Layer (USB PHY), Serial Interface Engine (SIE), and the local 512-byte memory buffer. USB Block Arbiter CPU/DMA...
Page 583: Arbiter
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.2.3 Arbiter The Arbiter handles access of the SRAM memory by the endpoints. The SRAM memory can be accessed by the CPU, DMA, or SIE. The arbiter handles the arbitration between the CPU, DMA, and SIE. The arbiter consists of the following blocks: •...
Page 584: Usb Phy
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode • Use external clock (EXTCLK) with the required accuracy 32.3.2 USB PHY The USB includes the transmitter and receiver (transceiver), which corresponds to the USB PHY. Figure 32-2 shows the PHY architecture.
Page 585: Usb D+ Pin Pull-Up Enable Logic
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.3.2.3 USB D+ pin pull-up enable logic When a USB device is self-powered, the USB specification warrants that the device enable the pull-up resistor on its D+ pin to identify itself as a full-speed device to the host. When the host VBUS is removed, the device should disable the pull-up resistor on the D+ line to not back power the host.
Page 586: Transfer Types
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.3.4 Transfer types The PSoC™ 6 MCU USB supports full-speed transfers and is compliant with the USB 2.0 specification. It supports four types of transfers: • Interrupt Transfer •...
Page 587: Data Endpoint Interrupt Events
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.3.5.3 Data endpoint interrupt events These are eight interrupt events corresponding to each data endpoint (EP1-EP8). Each of the endpoint interrupt events can be enabled/disabled by using the corresponding bit in the USBDEV_SIE_EP_INT_EN register. The interrupt status of each endpoint can be known by reading the USBDEV_SIE_EP_INT_SR status register.
Page 588: Arbiter Interrupt Event
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.3.5.7 Arbiter interrupt event The arbiter interrupt can arise from five possible sources. Each interrupt source is logically ANDed with its corresponding ENABLE bit and the results are logically ORed to result in a single arbiter interrupt event. The arbiter interrupt event can arise under any of the following five scenarios: •...
Page 589: Dma Support
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode either the DMA transfer descriptor transfer size or the USBDEV_DMA_THRESH and USBDEV_DMA_THRESH_MSB registers. – In an OUT endpoint, the common area overflow occurs when the data written to the common area has not yet been read and new data overwrites the existing data.
Page 590 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Table 32-1 gives a comparison of the two transfer modes. Table 32-1. USB transfer modes Feature Store and Forward mode Cut Through mode SRAM Memory Requires more memory Requires less memory Usage SRAM Memory...
Page 591 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Table 32-2. Endpoint registers (continued) Register Comment Content Usage USBDEV_ARB_RWx_DR Endpoint Data 8-Bit Data Data register is read/written to perform any Register transaction. IN command: Data written to the data register is copied to the SRAM location specified by the WA register.
Page 592: Manual Memory Management With No Dma Access
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.4.1 Manual memory management with no DMA access All operations in this mode are controlled by the CPU and works in a store-and-forward operation mode. An entire packet is transferred to the memory and a mode bit (such as ACK IN or ACK OUT) is set by the CPU.
Page 593: Manual Memory Management With Dma Access
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Set Base address to WA Set Packet size in the Endpoint byte count register Set mode in CR0 register Wait Is OUT Responds automatically Token Received? with ACK Data received from host Written to SRAM location WA WA++...
Page 594 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Write WA register (based on required memory allocation) Set Packet size in the Endpoint byte count register Set the DMA request in USBDEV_ARB_EPx_CFG register Value automatically written to the SRAM specified by WA DMA writes data to Endpoint Data Register WA++...
Page 595 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Write WA register (based on the required memory allocation) Set Packet size in the Endpoint byte count register Set mode in CR0 register Wait Is OUT Responds automatically with ACK Token Received? Data received from host Written to SRAM location WA...
Page 596: Automatic Dma Mode
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.4.3 Automatic DMA mode This is the Automatic memory management mode with auto DMA access. The CPU programs the initial buffer size requirement for IN/OUT packets and informs the arbiter block of the endpoint configuration details for the particular application.
Page 597 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Set Packet size in the Endpoint byte count register Set IN_DATA_RDY for the endpoint in ARB_EP1_CFG register This memory location is very limited. The memory location is filled initially to make sure Block automatically raises interrupt the host does not stall when an IN command is for DMA...
Page 598: Control Endpoint Logical Transfer
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Write maximum bytes to Byte Count register Program the Mode register for the endpoint Wait Is OUT Token Received? The DMA writes the received data to the SRAM in location specified by WA WA++ Is data in...
Page 599 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Set the mode bits to ACK the IN token Is SETUP token received? The block ACKs it Generates Interrupt and sets the bit in EP0_CR register to indicate that SETUP token was received Read the status bit and data valid Is Data Valid?
Page 600 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Program the mode bits for ACK_OUT Is SETUP token received? The block ACKs it Generates Interrupt and sets the bit in EP0_CR register to indicate that SETUP token was received Read the data valid bit in EP0_CNT Is Data Valid? Read the EP0_DRx register to find the type of...
Page 601: Usb Power Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode 32.5 USB power modes The USB supports two modes of operation: • Active mode: In this mode, the USB is powered up and clocks are turned on. •...
Page 602 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Universal Serial Bus (USB) device mode Table 32-3. USB registers (continued) Name Description USBDEV_EP_TYPE Endpoint type (IN/OUT) indication register USBDEV_ARB_EPx_CFG Endpoint configuration register USBDEV_ARB_EPx_INT_EN Endpoint interrupt enable register USBDEV_ARB_EPx_SR Endpoint interrupt enable register USBDEV_ARB_CFG Arbiter configuration register USBDEV_USB_CLK_EN...
Page 603: Lcd Direct Drive
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive LCD direct drive This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 604: Drive Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive • Duty: A driver is said to operate in 1/M duty when it drives ‘M’ number of COM electrodes. Each COM electrode is effectively driven 1/M of the time. • Bias: A driver is said to use 1/B bias when its waveforms use voltage steps of (1/B) ×...
Page 605 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive GPIO Output Impedance ITO Panel Resistance LCD Segment Capacitance PWM Generator PWM Generator DDDD 2/3 V 1/3 V Figure 33-1. PWM drive (at 1/3 Bias) The output waveform of the drive electronics is a PWM waveform. With the Indium Tin Oxide (ITO) panel resistance and the segment capacitance to filter the PWM, the voltage across the LCD segment is an analog voltage, as shown in Figure...
Page 606 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive One frame of Type A waveform (addresses all segments once) COM0 1/2 V COM1 1/2 V SEG0 1/2 V SEG1 1/2 V One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0) Segment On:...
Page 607 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive One frame of Type B waveform (addresses all segments twice) COM0 1/2 V COM1 1/2 V SEG0 1/2 V SEG1 1/2 V One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0) Segment On:...
Page 608 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive One ‘Frame’ of Type A Waveform (addresses all segments once) 2/3 V COM0 1/3 V 2/3 V COM1 1/3 V 2/3 V SEG0 1/3 V 2/3 V SEG1 1/3 V One Frame COM / SEG is selected COM / SEG is not selected...
Page 609 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive One ‘Frame’ of Type B Waveform (addresses all segments twice) 2/3 V COM0 1/3 V 2/3 V COM1 1/3 V 2/3 V SEG0 1/3 V 2/3 V SEG1 1/3 V One Frame COM / SEG is selected COM / SEG is not selected...
Page 610: Digital Correlation
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive The effective RMS voltage for ON and OFF segments can be calculated easily using these equations:     2 B 2 – 2 M 1 –   ...
Page 611 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive One ‘Frame’ of Type A Waveform (addresses all segments once) COM0 COM1 SEG0 SEG1 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0) Segment On: COM0 -SEG0...
Page 612 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive One ‘Frame’ of Type B Waveform (addresses all segments twice) COM0 COM1 SEG0 SEG1 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0) Segment On: COM0 -SEG0...
Page 613: Recommended Usage Of Drive Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive The RMS voltage applied to on and off segments can be calculated as follows:   –     RMS OFF ------------------ -   –   ...
Page 614: Psoc™ 6 Mcu Segment Lcd Direct Drive
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive Two Frames of of Type A Waveform with Dead-time (Example for 1/4 Duty and 1/3 bias) 2/3 V COM0 1/3 V 2/3 V COM1 1/3 V 2/3 V SEG0 1/3 V 2/3 V SEG1 1/3 V...
Page 615: High-Speed And Low-Speed Master Generators
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive The multiplexer selects one of these two generator outputs to drive LCD, as configured by the firmware. The LCD pin logic block routes the COM and SEG outputs from the generators to the corresponding I/O matrices. Any GPIO can be used as either COM or SEG.
Page 616: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture LCD direct drive (MMIO) and accessed through the AHB slave interface. See the PSoC™ 61 datasheet/ PSoC™ 62 datasheet for the pin connections. Table 33-2. SEG-COM mapping example of LCD0_DATA00 register (each SEG is a pin of the LCD port) BITS[31:28] = PIN_7[3:0] BITS[27:24] = PIN_6[3:0] PIN_7-COM3 PIN_7-COM2 PIN_7-COM1 PIN_7-COM0 PIN_6-COM3 PIN_6-COM2 PIN_6-COM1 PIN_6-...
Page 617: Analog Subsystem
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Analog subsystem Section E: Analog subsystem This section encompasses the following chapters: • “Analog reference block” on page 618 • “Low-power comparator” on page 621 • “SAR ADC” on page 627 • “Temperature sensor” on page 642 •...
Page 618: Analog Reference Block
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Analog reference block Analog reference block This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 619: Bandgap Reference Block
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Analog reference block Current mirror circuits are used to generate multiple current references to drive to different analog blocks. The following sections explain the configurations in detail. 34.2.1 Bandgap reference block The AREF block contains a local bandgap reference generator, which has tighter accuracy, temperature stability, and lower noise than the SRSS bandgap reference.
Page 620: Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Analog reference block 34.3 Registers Table 34-5. List of AREF registers Register Comment Features PASS_AREF_AREF_CTRL AREF control register Reference selection, startup time, and low- power mode. Reference manual 002-27293 Rev. *E 2023-09-06...
Page 621: Low-Power Comparator
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Low-power comparator Low-power comparator This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 622: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Low-power comparator 35.2 Architecture Figure 35-1 shows the block diagram for the Low-Power comparator. Low-Power comparator Block MMIO Analog Sub-Section Interface Registers Routing Comparator0 Switches dsi_comp0 inp0 edge + pulse (To HSIOM or trigger Sync multiplexer) inn0...
Page 623: Output And Interrupt Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Low-power comparator 35.2.2 Output and interrupt configuration Both Comparator0 and Comparator1 have hardware outputs available at dedicated pins. See the PSoC™ 61 datasheet/ PSoC™ 62 datasheet for the location of comparator output pins. Firmware readout of Comparator0 and Comparator1 outputs are available at the OUT0 and OUT1 bits of the LPCOMP_STATUS register (Table...
Page 624: Power Mode And Speed Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Low-power comparator Table 35-1. Output and interrupt configuration (continued) Register[Bit_Pos] Bit_Name Description LPCOMP_INTR[1] COMP1 Comparator1 Interrupt: hardware sets this interrupt when Comparator1 triggers. Write a '1' to clear the interrupt LPCOMP_INTR_SET[0] COMP0 Write a '1' to trigger the software interrupt for Comparator0 LPCOMP_INTR_SET[1] COMP1 Write a 1 to trigger the software interrupt for Comparator1...
Page 625: Hysteresis
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Low-power comparator 35.2.4 Hysteresis For applications that compare signals close to each other and slow changing signals, hysteresis helps to avoid oscillations at the comparator output when the signals are noisy. For such applications, a fixed hysteresis may be enabled in the comparator block.
Page 626: Register List
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Low-power comparator 35.3 Register list Table 35-4. Low-power comparator register summary Register Function LPCOMP_CONFIG LPCOMP global configuration register LPCOMP_INTR LPCOMP interrupt register LPCOMP_INTR_SET LPCOMP interrupt set register LPCOMP_INTR_MASK LPCOMP interrupt request mask register LPCOMP_INTR_MASKED LPCOMP masked interrupt output register LPCOMP_STATUS...
Page 627: Sar Adc
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC SAR ADC This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 628: Architecture
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2 Architecture External Reference or Bypass Capacitor for Buffer Internal Reference 1.2V from AREF Pin 0 Pin 1 Pin 2 SAR_CTRL Pin 3 Pins of SARMUX Port Pin 4 Pin 5 SAR_CHAN_WORK_UPDATED SAR_CHAN_RESULT_UPDATED PLUS...
Page 629: Single-Ended And Differential Modes
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.1.1 Single-ended and differential modes The PSoC™ 6 MCU SAR ADC can operate in single-ended and differential modes. Differential or single-ended mode can be configured using the DIFFERENTIAL_EN bitfield in the channel configuration register, SAR_CHAN_CONFIGx, where x is the channel number (0–15).
Page 630: Result Data Format
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.1.3 Result data format Result data format is configurable from two aspects: • Signed/unsigned • Left/right alignment When the result is considered signed, the most significant bit of the conversion is used for sign extension to 16 bits with MSb.
Page 631: Negative Input Selection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.1.4 Negative input selection The negative input connection choice affects the voltage range and effective resolution (Table 36-2). In single- ended mode, negative input of the SAR ADC can be connected to V , or P1, P3, P5, or P7 pins of SARMUX.
Page 632: Acquisition Time
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.1.5 Acquisition time Acquisition time is the time taken by sample and hold (S/H) circuit inside SAR ADC to settle. After acquisition time, the input signal source is disconnected from the SARADC core, and the output of the S/H circuit will be used for conversion.
Page 633: Sar Adc Timing
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.1.7 SAR ADC timing Figure 36-4 shows, an ADC conversion with the minimum acquisition time of four clocks requires 18 clocks to complete. Note that the minimum acquisition time of four clock cycles at 36 MHz is based on the minimum acquisition time supported by the SAR block (R and C Figure...
Page 634: Analog Routing
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.2.1 Analog routing SARMUX has many switches that may be controlled by SARSEQ block (sequencer controller) or firmware. Different control methods have different control capability on the switches. Figure 36-5 shows the SARMUX switches.
Page 635: Sarref
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC Input from SARMUX port In this mode, sequencer and firmware control are possible. In addition to SARMUX switch configuration, the GPIOs must be configured properly to connect to SARMUX. See the “I/O system”...
Page 636: Reference Buffer And Bypass Capacitors
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.3.2 Reference buffer and bypass capacitors The internal references, 1.2 V from bandgap and V /2, are buffered with the reference buffer. This reference may be routed to the external V pin where a capacitor can be used to filter noise that may exist on the reference.
Page 637: Channel Configuration
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC – One of four programmable acquisition times – Result averaging and accumulation • Scan triggering – One-shot, periodic, or continuous mode – Triggered by any digital signal or input from GPIO pin –...
Page 638: Range Detection
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC take N consecutive samples of the specified channel before moving to the next channel. In the interleaved mode, one sample is taken per channel and averaged over several scans. 36.2.4.3 Range detection The SARSEQ supports range detection to allow automatic detection of result values compared to two programmable thresholds without CPU involvement.
Page 639: End-Of-Scan Interrupt (Eos_Intr)
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.2.5.1 End-of-scan interrupt (EOS_INTR) After completing a scan, the end-of-scan interrupt (EOS_INTR) is raised. Firmware should clear this interrupt after picking up the data from the RESULT registers. EOS_INTR can be masked by making the EOS_MASK bit 0 in the SAR_INTR_MASK register. EOS_MASKED bit of the SAR_INTR_MASKED register is the logic AND of the interrupt flags and the interrupt masks.
Page 640: Interrupt Cause Overview
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC Saturation interrupt flag is set immediately to enable a fast response to saturation, before the full scan and averaging. Saturation detection interrupt for specified channel can be masked by setting the SAR_SATURATE_INTR_MASK register specified bit to ‘0’.
Page 641: Registers
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture SAR ADC 36.3 Registers Table 36-5. Registers Register name Description SAR_CTRL Global configuration register. Analog control register SAR_SAMPLE_CTRL Global configuration register. Sample control register SAR_SAMPLE_TIME01 Global configuration register. Sample time specification ST0 and ST1 SAR_SAMPLE_TIME23 Global configuration register.
Page 642: Temperature Sensor
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Temperature sensor Temperature sensor This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 643 PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Temperature sensor • ‘A’ is the 16-bit multiplier constant. The value of A is determined using the PSoC™ 6 MCU characterization data of two point slope calculation. It is calculated as given in the following equation. –...
Page 644: Sar Adc Configuration For Measurement
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture Temperature sensor Note: A and B are 16-bit constants stored in flash during factory calibration. These constants are valid only with a specific SAR ADC configuration. See “SAR ADC configuration for measurement” on page 644 for details.
Page 645: Capsense
PSoC™ 61, PSoC™ 62 MCU: CY8C6xx5 architecture CAPSENSE™ CAPSENSE™ The CAPSENSE™ system can measure the self-capacitance of an electrode or the mutual capacitance between a pair of electrodes. In addition to capacitive sensing, the CAPSENSE™ system can function as an ADC to measure voltage on any GPIO pin that supports the CAPSENSE™...
Page 646: Revision History
Aligned the Introduction section with the datasheet. 2020-06-30 Added information about CY8C61x5 devices Updates throughout the document to address review comments. Migrated to Infineon template. Fixed typos: Sflash to SFlash, AUXflash and EE emulation to AUXFlash. Updated PSoC™ 6 Programming Specification weblink. 2023-06-19...
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