Table of Contents
Advertisement
1.
The system clock period T must be greater than T
2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t
and t
are specified with respect to T.
LC
3. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal.
So long as the minimum periods are greater than 0.35T
4. Because the delay (t
dtr
can result in t
not exceeding t
dtr
greater than or equal to zero, so long as the clock rise-time t
5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always
giving the receiver sufficient setup time.
6. The data setup and hold time must not be less than the specified receiver setup and hold time.
Note: The time periods specified in
match transmitter performance.
SCK
SD and WS
T = Clock period
T
= Minimum allowed clock period for transmitter
tr
T = T
tr
* t
is only relevant for transmitters in slave mode.
RC
Document Number: 002-14949 Rev. *G
PRELIMINARY
and T
because both the transmitter and receiver have to be able to handle the data transfer rate.
tr
r
) and the maximum transmitter speed (defined by T
which means t
becomes zero or negative. Therefore, the transmitter has to guarantee that t
RC
htr
Figure 14
and
Figure 15
Figure 14. I
T
t
*
RC
t
> 0
htr
t
< 0.8T
otr
, any clock that meets the requirements can be used.
r
) are related, a fast transmitter driven by a slow clock edge
tr
is not more than t
RC
RCmax
are defined by the transmitter speed. The receiver specifications must
2
S Transmitter Timing
t
> 0.35T
LC
, where t
is not less than 0.15T
RCmax
t
> 0.35T
HC
CYW43353
HC
is
htr
.
tr
V
= 2.0V
H
V
= 0.8V
L
Page 37 of 113
Advertisement
Table of Contents
