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6. Global Functions
6.1 External Coexistence Interface
An external handshake interface is available to enable signaling between the device and an external colocated wireless device, such
as Bluetooth, to manage wireless medium sharing for optimum performance.
Figure 7
shows the coexistence interface.
WLAN
NOTES:
SECI_OUT/BT_TXD and SECI_IN/BT_RXD are multiplexed on the GPIOs.
The 2‐wire coexistence interface is intended for future compatibility with the BT SIG 2‐wire interface that is being standardized for Core 4.1.
Note: SECI UART is the same as UART2, one of the low-speed UART interfaces mentioned in section 5.7 and in the reference
schematics.
6.2 One-Time Programmable Memory
Various hardware configuration parameters can be stored in an internal 6144-bit (768 bytes) One-Time Programmable (OTP) memory
that is read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and
MAC address can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP memory device is 0. After any bit is programmed to a 1, it cannot be reprogrammed
to 0. The entire OTP memory array can be programmed in a single write-cycle using a utility provided with the Cypress WLAN
manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits that are
still in the 0 state can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file. The nvram.txt file is
provided with the reference board design package.
6.3 Hibernation Block
The Hibernation (HIB) block is a self-contained power domain that can be used to completely shut down the rest of the CYW43903.
This optional block uses the HIB_REG_ON_OUT pin to drive the REG_ON pin. Therefore, for the HIB block to work as designed, the
HIB_REG_ON_OUT pin must be connected to the REG_ON pin. To use the HIB block, software programs the HIB block with a wake
count and then asserts a signal indicating that the chip should be put into hibernation. After assertion, the HIB block drives
HIB_REG_ON_OUT low for the number of 32 kHz clock cycles programmed as the wake count. After the wake-count timer expires,
HIB_REG_ON_OUT is driven high. Other than the logic state of the HIB block, no state is saved in the CYW43903 during hibernation.
Document Number: 002-14826 Rev. *G
PRELIMINARY
Figure 7. Cypress 2-Wire External Coexistence Interface
CYW43903
SECI_OUT
GCI
SECI_IN
CYW43903
BT\IC
UART_IN
UART_OUT
Page 20 of 65
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