Virtex-5 Fpga; Configuration; I/O Voltage Rails - Xilinx ML50 Series User Manual

Chapter 1: ML501 Evaluation Platform

1. Virtex-5 FPGA

A Xilinx Virtex-5 FPGA, XC5VLX50-1FFG676, is installed on the Evaluation Platform (the
board).

Configuration

The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master
SelectMAP, Slave SelectMAP, Byte-wide Peripheral Interface (BPI) Up, BPI Down, and SPI
modes. See the

I/O Voltage Rails

The FPGA has 14 banks. The I/O voltage applied to each bank is summarized in
Table 1-1: I/O Voltage Rail of FPGA Banks
14
"Configuration Options," page 36
FPGA Bank
0 3.3V
1 3.3V
2 3.3V
3 2.5V
4 3.3V
11 User selectable as 2.5V or 3.3V using jumper J20
12 3.3V
13 User selectable as 2.5V or 3.3V using jumper J20
14 1.8V
15 3.3V
16 1.8V
17 3.3V
18 1.8V
21 1.8V
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section for more information.
I/O Voltage Rail
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
R
Table 1-1.