Sfr Definition 26.3. Eie1 - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 26.3. EIE1

Bit 7
Name Reserved Reserved
R
Type
0
Reset
SFR Address = 0xE6
Bit Name
7:5 Reserved Read as 0x0. Write has no effect.
Enable VOID1 Interrupt (Reserved).
This bit sets the VOID1 interrupt.(Reserved)
4 EVOID1
0: Disable VOID1 interrupts.
1: Enable interrupt requests generated by VOID1 flags (Reserved).
Enable VOID0 Interrupt (Reserved).
This bit sets the VOID0 interrupt.(Reserved)
3 EVOID0
0: Disable VOID0 interrupts.
1: Enable interrupt requests generated by VOID0 flags (Reserved).
Enable Frequency Counter Interrupt.
This bit sets the Frequency Counter interrupt.
2 EFC
0: Disable Frequency Counter interrupt.
1: Enable interrupt requests generated by Frequency Counter.
1:0 Reserved Reset value 0x0 must not be changed.
96
6 5 4
Reserved EVOID1
R R R/W
0 0 0
Rev. 1.0
3 2
EVOID0 EFC Reserved
R/W R/W
0 0
Function
1 0
Reserved
R R
0 0