Sfr Definition 15.2. Sysgen - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 15.2. SYSGEN

Bit 7
Name SYSGEN_ Re-served PWR_1ST
SHUT-
DOWN
R/W
Type
0
Reset
SFR Address = 0xBE
Bit Name
System General Shutdown.
Setting this bit causes shutdown of MCU and most analog. Recovery from this is via 
SYSGEN_
falling edge on any GPIO, which results in a power up and a power on reset. This is
SHUT-
7
THE bit that shuts down the power to nearly everything.
DOWN
0: Normal operation
1: Shutdown. Do not use this bit directly. It is recommended to use the
vSys_Shutdown() API call.
6 Reserved Read as 0. Write has no effect.
PWR_1ST_ Initial Powerup Indicator.
5
TIME
Read only register. It will get set when power up was caused by a battery insertion.
Real Time Clock Clear.
RTC_
4
0: Normal operation
TICKCLR
1: Clears the real time clock 5.12us counter.
Port Hold.
This bit needs to be set before shutting down, it delays any button pushes that occur
PORT_
between this bit setting and shutdown until the chip completes shutdown, to ensure
3
HOLD the shutdown process cannot be interrupted.
0: Normal operation
1: Holds GPIO port values until shutdown is complete
System Clock Generator Divider.
System clock divider control to generate the system clock.
000: 24 MHz; div = 1
001: 12 MHz; div = 2
SYSGEN_
010: 6.0 MHz; div = 4
2:0
DIV[2:0]
011: 3.0 MHz; div = 8
100: 1.5 MHz; div = 16
101: 0.75 MHz; div = 32
110: 0.375 MHz; div = 64
111: 0.1875 MHz; div = 128
48
6 5 4
RTC_
_TIME
TICKCLR
R R W
0 — 0
Rev. 1.0
3 2
PORT_ SYSGEN_DIV[2:0]
HOLD
R/W
0 0
Function
1 0
R/W
0 0