Interrupt Register Descriptions; Table 26.1. Interrupt Summary - Silicon Laboratories Si4010-C2 Manual

Interrupt Source
Reset
External INT 0 (INT0)
Timer 2 Overflow
Temp Sensor DMD
Real Time Clock Tick
ODS Ready for Data
Timer 3 Overflow
External INT1
Reserved
Reserved
Frequency Counter Count
Done
Software Source 0 
(can be used for software
generated interrupts)
Software Source 1 
(can be used for software
generated interrupts)

26.4. Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).

Table 26.1. Interrupt Summary

Interrupt Priority
Vector Order
0x0000 Top
0x0003 0
0x000B 1
0x0013 2
0x001B 3
0x0023 4
0x002B 5
0x0033 6
0x003B 7
0x0043 8
0x004B 9
0x0053 10
0x005B 11
Rev. 1.0
Pending Flag
None N/A
INT0_FLAG N
(INT_FLAGS.0)
TMR2INTL Y
(TMR2CTRL.6)
TMR2INTH
(TMR2CTRL.7)
DMD_NEW N
(DMD_CTRL.3)
RTC_INT N
(RTC_CTRL.7)
ODS_FLAG N
(INT_FLAGS.2)
TMR3INTL N
(TMR3CTRL.6)
TMR3INTH
(TMR3CTRL.7)
INT1_FLAG N
(INT_FLAGS.1)
N/A N/A
N/A N/A
FC_DONE N
(FC_CTRL.7)
VOID0_FLAG N
(INT_FLAGS.3)
VOID1_FLAG N
(INT_FLAGS.4)
Si4010-C2
Enable Flag Priority
Control
Always Always
Enabled Highest
EINT0 (IE.0) PINT0 (IP.0)
ETMR2 PTMR2
(IE.1) (IP.1)
EDMD (IE.2) PDMD (IP.2)
ERTC (IE.3) PRTC (IP.3)
EODS (IE.4) PODS (IP.4)
ETMR3 PTMR3
(IE.5) (IP.5)
EINT1 (IE.6) PINT1 (IP.6)
N/A N/A
N/A N/A
EFC PFC
(EIE1.2) (EIP1.2)
EVOID0 PVOID0
(EIE1.3) (EIP1.3)
EVOID1 PVOID1
(EIE1.4) (EIP1.4)
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