Sfr Definition 30.2. P0Con; Sfr Definition 30.3. P1 - Silicon Laboratories Si4010-C2 Manual

SFR Definition 30.2. P0CON

Bit 7
Name
R/W R/W
Type
0
Reset
SFR Address = 0xA4
Bit Name
Port 0 Configuration Register, for GPIO[7:0].
This bit controls configuration of each corresponding output bit in P0.
0 .. open-drain
7:0 P0CON[7:0]
1 .. push-pull
If the pin to be input, it must be configured as open-drain and 1 has to be written as
output value to it.

SFR Definition 30.3. P1

Bit 7
Name
R/W R/W
Type
0
Reset
SFR Address = 0x90
Bit Name
Port 1 Register GPIO[15:8], Bit Addressable.
Write appears at the GPIO[15:8] outputs, read reads directly the GPIO input values.
7:0 P1[7:0]
Same as for P0. Only GPIO[9:8] are used, write to the rest of the register has no
effect, read returns 0 at those bits.
6 5 4
P0CON[7:0]
R/W R/W
0 0 0
6 5 4
R/W R/W
0 0 0
Rev. 1.0
3 2
R/W R/W
0 0
Function
3 2
P1[7:0]
R/W R/W
0 0
Function
Si4010-C2
1 0
R/W R/W
0 0
1 0
R/W R/W
1 1
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