Sfr Definition 34.3. Tmr2Rl; Sfr Definition 34.4. Tmr2Rh - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 34.3. TMR2RL

Bit 7
Name
Type
0
Reset
SFR Address = 0xCA
Bit Name
Timer 2 Capture/Reload Register Low Byte.
TMR2RL holds the low byte of the capture/reload value for Timer 2. LSB Byte. Two
halves are not double buffered. Write to each of the halves takes effect immedi-
7:0 TMR2RL[7:0]
ately. If the timer or respective half operates in capture mode this register holds the
capture value. If the timer or respective half operates in timer mode this register
holds the reload value.

SFR Definition 34.4. TMR2RH

Bit 7
Name
Type
0
Reset
SFR Address = 0xCB
Bit Name
Timer 2 Capture/Reload Register High Byte.
7:0 TMR2RH[7:0]
TMR2RH holds the high byte of the reload value for Timer 2.
142
6 5 4
TMR2RL[7:0]
0 0 0
6 5 4
TMR2RH[7:0]
0 0 0
Rev. 1.0
3 2
R/W
0 0
Function
3 2
R/W
0 0
Function
1 0
0 0
1 0
0 0