Sfr Definition 30.7. Port_Set - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 30.7. PORT_SET

Bit 7
EDGE_ EDGE_
Name
INT1 INT0
R/W R/W
Type
0
Reset
SFR Address = 0xB6
Bit Name
Edge Control for INT1.
EDGE_
This bit controls whether single edge or both edges invoke the interrupt.
7 INT1
0: Single edge, polarity specified by NEG_INT1 in PORT_INTCFG.
1: Both edges, which means any edge, invoke INT1 interrupt.
Edge Control for INT0.
EDGE_
This bit controls whether single edge or both edges invoke the interrupt.
6 INT0
0: Single edge, polarity specified by NEG_INT0 in PORT_INTCFG.
1: Both edges, which means any edge, invoke INT0 interrupt.
Select which GPIO Pin is used as Clock Output Pin.
PORT_
PORT_CLKOUT[0]: 1 .. clk output at GPIO[4], 0 .. normal/other GPIO[4] operation
CLKOUT
PORT_CLKOUT[1]: 1 .. clk output at GPIO[6], 0 .. normal/other GPIO[6] operation
5:4
[1:0]
Both outputs can be used simultaneously. The actual clock waveform can be
enabled/disabled by port_clken bit, but the GPIO configuration is purely controlled by
PORT_CLKOUT.
Enable Output Clock, Which is Possibly Coming out on GPIO[4] and/or
GPIO[6].
This bit is just a clock enable/disable, it does not configure the GPIO for clock out-
PORT_
3
puts. The port configuration must be done by port_clkout below. The generated clock
CLKEN
division is controlled by CLKOUT_SET register. If the clock is disabled by
PORT_CLKEN=0 the current period in progress will be finished and the output clock
will stop as logic 0.
Enable CLK_REF Reference Clock to come from GPIO[3].
PORT_
2
The GPIO[3] pad is forced to be an input. There is not need to change p0 or p0con
REFEN
register values, since port_refen has higher priority.
1:0 Reserved These bits must be left at 0.
122
6 5 4
PORT_CLKOUT[1:0]
R/W R/W
0 0 0
Rev. 1.0
3 2
PORT_ PORT_ Reserved
CLKEN REFEN
R/W R/W
0 0
Function
1 0
Reserved
R/W R/W
0 0