Silicon Laboratories Si4010-C2 Manual

Silicon Laboratories Si4010-C2 Manual

Crystal-less soc rf transmitter
Table of Contents

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C
-
R YS TA L
L E S S
Features
Crystal-less operation
Optional crystal oscillator input

High-Speed 8051 µC Core
Pipeline instruction architecture

70% of instructions in 1 or 2 clocks

Up to 24 MIPs with 24 MHz clock

4 kB RAM/8kB NVM

128 bit EEPROM

256 byte of internal data RAM

12 kB ROM embedded functions

8 byte low leakage RAM

Extensive Digital Peripherals
128 bit AES accelerator

5/9 GPIO with wakeup functionality

LED driver

Data serializer

High-speed frequency counter

On-chip debugging: C2

Unique 4 byte serial number

Ultra low-power sleep timer

Applications
Garage and gate door openers
Remote keyless entry
Description
The Si4010 is a fully integrated crystal-less CMOS SoC RF transmitter with an
embedded CIP-51 8051 MCU. The device can operate over the –40 to 85 °C
temperature range without requiring an external crystal reference source reducing
board area and BOM cost. The device includes an 8 kB non volatile memory block
for programming the user's application along with a 12 kB ROM of embedded
support code for use in the user's application. The Si4010 includes Silicon
Laboratories' 2-wire C2 Debug and Programming interface, which allows
customers to download their code during the development stage into the on-board
RAM for testing and debug prior to programming the NVM.
The Si4010 is designed for low power battery applications with standby currents of
less than 10 nA to optimize battery life and features automatic wake on button
press support to efficiently move from the standby to active mode state with
minimal customer code support. Built in AES-128 hardware encryption along with
a 128-bit EEPROM can be used to create robust data encryption of the
transmitted packets. A unique 4-byte serial number is programmed into each
device ensuring non-overlapping device identifiers.
The RF transmitter features a high efficiency PA capable of delivering output
power up to +10 dBm and includes an automatic antenna tuning algorithm. This
algorithm adjusts the antenna tuning at the start of each packet transmission for
optimal output power minimizing the impact of antenna impedance changes due
to the remote being held in a user hand. The devices supports FSK and OOK
modulations and includes automatic output power shaping to reduce spectral
spreading and ease regulatory compliance. The output frequency can be adjusted
via software over the entire 27 to 960 MHz range. The output data rate is software
adjustable up to a maximum rate of 100 kbps.
Rev. 1.0 2/11
S
C RF T
O
R A N S M I T T E R
Single Coin-Cell Battery Operation
Supply voltage: 1.8 to 3.6 V

Standby current < 10 nA

High-performance RF transmitter
Frequency range: 27–960 MHz

+10 dBm output power,

adjustable
Automatic antenna tuning

Symbol rate up to 100 kbps

FSK/OOK modulation

Manchester, NRZ, 4/5 encoder

Analog Peripherals
LDO regulator with POR circuit

Battery voltage monitor

Temperature range –40 to +85 °C
Automotive quality option, 
AEC-Q100 (Pending final
qualification testing)
10-pin MSOP/14-pin SOIC
Home automation and security
Wireless remote controls
Copyright © 2011 by Silicon Laboratories
S i 4 0 1 0 - C 2
Ordering Information:
See page 15.
Pin Assignments
GPIO0/XTAL
1
GND
2
Si4010-GT
TXM
3
TXP
4
VDD
5
10-Pin MSOP
GPIO9 1
VPP/GPIO0/XTAL
2
GND
3
Si4010-GS
TXM
4
TXP
5
VDD
6
GPIO7
7
14-Pin SOIC
Patents pending
10 GPIO1
9 GPIO2
8
GPIO3
7
GPIO4
6
LED
14 GPIO8
13 GPIO1
12 GPIO2
11
GPIO3
10
C2DAT/GPIO4
9
C2CLK/LED
8
GPIO6
Si4010

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Summary of Contents for Silicon Laboratories Si4010-C2

  • Page 1 The output frequency can be adjusted via software over the entire 27 to 960 MHz range. The output data rate is software adjustable up to a maximum rate of 100 kbps. Rev. 1.0 2/11 Copyright © 2011 by Silicon Laboratories Si4010...
  • Page 2 Si4010-C2 Functional Block Diagram Si4010 LDO REGULATOR CR2032 COIN CELL 1.8 – 3.6 V LOOP DIVIDER ANTENNA INTEGRATED 8051 MCU RAM/ EEPROM GPIO INTERFACE 8 Kbyte 128-bit PUSH BUTTONS Rev. 1.0...
  • Page 3: Table Of Contents

    Si4010-C2 ABLE O F ONTENTS 1. System Overview............11 2.
  • Page 4 Si4010-C2 22.1. Instruction Set ........... . .56 22.1.1.
  • Page 5 Si4010-C2 30. Port Input/Output............108 30.1.
  • Page 6 Si4010-C2 I S T OF IGURES Figure 1.1. Si4010 Block Diagram .................... 12 Figure 2.1. Test Block Diagram with 10-Pin MSOP ..............13 Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator ........14 Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator ..14 Figure 1.
  • Page 7 Si4010-C2 I S T OF ABLES Table 4.1. Product Selection Guide ..................15 Table 1. Top Marking Explanation .................... 16 Table 2. Top Marking Explanation .................... 17 Table 7.1. Package Dimensions ....................22 Table 7.2. Package Dimensions ....................23 Table 8.1. 10-Pin MSOP Dimensions ..................25 Table 9.1.
  • Page 8 Si4010-C2 XREG R I S T OF EGISTERS XREG Definition 12.2. wPA_CAP ..................38 XREG Definition 12.3. bPA_TRIM ..................39 XREG Definition 15.1. bLPOSC_TRIM .................. 47 XREG Definition 16.1. bXO_CTRL ..................49 XREG Definition 17.3. IFC_COUNT ..................53 XREG Definition 23.1. abMTP_RDATA[16] ................68...
  • Page 9 Si4010-C2 SFR R I S T OF EGISTERS SFR Definition 12.1. PA_LVL ....................38 SFR Definition 13.1. ODS_CTRL ..................... 41 SFR Definition 13.2. ODS_TIMING ..................42 SFR Definition 13.3. ODS_DATA ..................... 43 SFR Definition 13.4. ODS_RATEL ................... 43 SFR Definition 13.5. ODS_RATEH ..................44 SFR Definition 13.6.
  • Page 10 Si4010-C2 SFR Definition 33.1. RTC_CTRL ................... 130 SFR Definition 34.1. TMR_CLKSEL ..................139 SFR Definition 34.2. TMR2CTRL ................... 140 SFR Definition 34.3. TMR2RL ....................142 SFR Definition 34.4. TMR2RH ....................142 SFR Definition 34.5. TMR2L ....................143 SFR Definition 34.6. TMR2H ....................143 SFR Definition 34.7.
  • Page 11: System Overview

    The Si4010 includes Silicon Laboratories' 2-wire C2 Debug and Programming interface. This debug logic supports memory inspection, viewing and modification of special function registers (SFR), setting break points, single stepping, and run and halt commands.
  • Page 12: Figure 1.1. Si4010 Block Diagram

    Si4010-C2 Si4010 CIP-51 8051 MEMORY RF ANALOG CORE CONTROLLER CORE CONTROLLER 256 BYTE IRAM EEPROM HVRAM 8 KB 128-bit 8 Byte 256 BYTE XREG 4K BYTE RAM 12K BYTE ROM DIGITAL PERIPHERALS AUTO DIVIDER INTC TUNE LCOSC TMR 2,3 LPOSC...
  • Page 13: Test Circuit

    Si4010-C2 2. Test Circuit 1 uF GPIO0 GPIO1 GPIO2 TESTER TEST MATCHING GPIO3 Si4010-GT INTERFACE EQUIPMENT NETWORK GPIO4 Figure 2.1. Test Block Diagram with 10-Pin MSOP Rev. 1.0...
  • Page 14: Typical Application Schematic

    Si4010-C2 3. Typical Application Schematic 3.1. Si4010 Used in a 5-Button RKE System with LED Indicator CR2032 COIN CELL 1.8 to 3.6 V GPI0 GPIO1 GPIO2 GPIO3 Si4010-GT GPIO4 LOOP ANTENNA Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator 3.2.
  • Page 15: Ordering Information

    Si4010-C2 4. Ordering Information Table 4.1. Product Selection Guide Si4010-C2-GT MSOP-10 — Si4010-C2-GS SOIC-14 — Si4010-C2-AT MSOP-10 Si4010-C2-AS SOIC-14 Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. 2. Assumes LED driver is used and no external crystal.
  • Page 16: Top Markings

    Si4010-C2 5. Top Markings 5.1. SOIC   Figure 1. Si4010 Top Marking Table 1. Top Marking Explanation Line Characters Description Circle = 1.1 mm Diameter "e3" Pb-Free Symbol Left-Justified Line 1 Customer Part Number Si4010C2 YY = Year Assigned by the Assembly House. Corresponds to the year and WW = Work Week work week of the assembly date.
  • Page 17: Msop

    Si4010-C2 5.2. MSOP   Figure 2. Si4010 Top Marking Table 2. Top Marking Explanation Line Characters Description Line 1 Device Part Number 10C2 Line 2 from the "Markings" section of the Assembly Purchase Line 2 TTTT = Trace Code Order form.
  • Page 18: Pin Definitions

    Si4010-C2 6. Pin Definitions 6.1. MSOP, Application GPIO0/XTAL 10 GPIO1 9 GPIO2 Si4010-GT GPIO3 GPIO4 Pin Number(s) Name Description GPIO0/XTAL General purpose input pin. Can be configured as an input pin for a crystal. Ground. Connect to ground plane on PCB.
  • Page 19: Msop, Programming/Debug Mode

    Si4010-C2 6.2. MSOP, Programming/Debug Mode VPP/GPIO0/XTAL 10 GPIO1 9 GPIO2 Si4010-GT GPIO3 C2DAT/GPIO4 C2CLK/LED Pin Number(s) Name Description +6.5 V required for NVM (OTP) Memory programming. Ground. Connect to ground plane on PCB. Transmitter differential output. Transmitter differential output. Power.
  • Page 20: Soic Package, Application

    Si4010-C2 6.3. SOIC Package, Application GPIO9 1 14 GPIO8 GPIO0/XTAL 13 GPIO1 12 GPIO2 Si4010-GS GPIO3 GPIO4 GPIO7 GPIO6 Name Description Number(s) GPIO9 General purpose input/output pin GPIO0/XTAL General purpose input pin. Can be configured as an input pin for a crystal Ground.
  • Page 21: Soic Package, Programming/Debug Mode

    Si4010-C2 6.4. SOIC Package, Programming/debug Mode GPIO9 1 14 GPIO8 VPP/GPIO0/XTAL 13 GPIO1 12 GPIO2 Si4010-GS GPIO3 C2DAT/GPIO4 C2CLK/LED GPIO7 GPIO6 Name Description Number(s) GPIO9 General purpose input/output pin +6.5 V required for NVM (OTP) Memory programming Ground. Connect to ground plane on PCB...
  • Page 22: Package Specifications

    Si4010-C2 7. Package Specifications 7.1. 10-Pin MSOP Figure 7.1 illustrates the package details for the Si4010, 10-pin MSOP package. Table 7.1 lists the values for the dimensions shown in the illustration. Figure 7.1. 10-Pin MSOP Package Table 7.1. Package Dimensions...
  • Page 23: 14-Pin Soic Package

    Si4010-C2 7.2. 14-pin SOIC Package Figure 7.2 illustrates the package details for the Si4010, 14-pin SOIC package. Table 7.2 lists the values for the dimensions shown in the illustration. Figure 7.2. 14-Pin SOIC Package Table 7.2. Package Dimensions Symbol Symbol —...
  • Page 24: Pcb Land Pattern 10-Pin Msop

    Si4010-C2 8. PCB Land Pattern 10-Pin MSOP Figure 8.1. 10-Pin MSOP Recommended PCB Land Pattern Rev. 1.0...
  • Page 25: Table 8.1. 10-Pin Msop Dimensions

    Si4010-C2 Table 8.1. 10-Pin MSOP Dimensions Dimension 4.40 REF 0.50 BSC 3.00 — — 0.30 1.40 REF — 5.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ASME Y14.5M-1994. 3. This Land Pattern Design is based on the IPC-7351 guidelines.
  • Page 26: Pcb Land Pattern 14-Pin Soic Package

    Si4010-C2 9. PCB Land Pattern 14-pin SOIC Package   Figure 9.1. 14-Pin SOIC Recommended PCB Land Pattern Rev. 1.0...
  • Page 27: Table 9.1. Pcb Land Pattern Dimensions

    Si4010-C2 Table 9.1. PCB Land Pattern Dimensions Dimension 5.30 5.40 1.27 BSC 0.50 0.60 1.45 1.55 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines.
  • Page 28: Electrical Characteristics

    Si4010-C2 10. Electrical Characteristics Table 10.1. Recommended Operating Conditions Parameter Symbol Test Condition Unit Supply Voltage — Supply Voltage Slew Rate Initial Battery Insertion* — Ambient Temperature –40 °C Digital Input Range Digital Input Signals –0.3 — *Note: Recommend bypass capacitor = 1 µF; slew rate measured 1 V < V ,<...
  • Page 29: Table 10.3. Dc Characteristics

    Si4010-C2 Table 10.3. DC Characteristics (TA = 25° C, VDD = 3.3 V, RL = 480, unless otherwise noted) Parameter Symbol Test Condition Unit Supply Current +10 dBm output, OOK, — 14.2 — Manchester +6.5 dBm output, OOK, — 11.3 —...
  • Page 30: Table 10.4. Si4010 Rf Transmitter Characteristics

    Si4010-C2 Table 10.4. Si4010 RF Transmitter Characteristics (TA = 25° C, VDD = 3.3 V, RL = 480,, SOIC package unless otherwise noted) Parameter Symbol Test Condition Unit Frequency Range — Frequency Noise (rms) Allen deviation, measured — — across 1 ms interval...
  • Page 31: Table 10.5. Low Battery Detector Characteristics

    Si4010-C2 Table 10.4. Si4010 RF Transmitter Characteristics(Continued) (TA = 25° C, VDD = 3.3 V, RL = 480,, SOIC package unless otherwise noted) Parameter Symbol Test Condition Unit Peak to Peak  Max frequency deviation — — FSK Deviation Deviation resolution —...
  • Page 32: Table 10.7. Eeprom Characteristics

    Si4010-C2 Table 10.7. EEPROM Characteristics Parameter Conditions Units Program Time Independent of number of bits — changing values Count per 32-Bit Counter Using API — 1000000 1000100 cycles Write Endurance (per bit)* 50000 — — cycles Note: *API uses coding technique to achieve write endurance of 1M cycles per bit.
  • Page 33: System Description

    Si4010-C2 11. System Description Si4010 CIP-51 8051 MEMORY RF ANALOG CORE CONTROLLER CORE CONTROLLER 256 BYTE IRAM EEPROM HVRAM 8 KB 128-bit 8 Byte 256 BYTE XREG 4K BYTE RAM 12K BYTE ROM DIGITAL PERIPHERALS AUTO DIVIDER INTC TUNE LCOSC...
  • Page 34 Si4010-C2 The Si4010 has three timing sources. The LCOSC is the most accurate timing source native to the chip. Each device is factory trimmed and programmed at Silicon Labs to produce a frequency accuracy of better than ±150 ppm over the temperature range of 0 to + 70 °C and ±250 ppm over the industrial range of –40 to +85 °C.
  • Page 35: Setting Basic Si4010 Transmit Parameters

    Si4010-C2 The Si4010 includes Silicon Laboratories' 2-wire C2 Debug and Programming interface. This debug logic supports inspection memory, viewing and modification of special function registers (SFR), setting break points, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging using C2.
  • Page 36: Power Amplifier

    Si4010-C2 12. Power Amplifier INPUT tail FEEDBACK (HW, SW) FREQUENCY TUNE, CONST PWR Figure 12.1. Simplified PA Block Diagram The CMOS power amplifier (PA) is a differential open drain amplifier capable of delivering +10 dBm of out- put power. Maximum power can be transferred to an inductive antenna load when the antenna and output...
  • Page 37 Si4010-C2 (PVT) to keep its quality factor (Q) nearly constant at 50 (at 434 MHz). The starting value of the 9-bit capacitor word (XREG PA_CAP) is chosen with the help of the calculator spreadsheet. In general, a high operating frequency requires a smaller capacitance and hence a low value capacitive word. The output resistance of the PA is a strong function of the capacitive word because the variable capacitor is imple- mented with a capacitor and a MOS switch.
  • Page 38: Register Description

    Si4010-C2 12.1. Register Description SFR Definition 12.1. PA_LVL PA_LVL_NSLICE[4:0] PA_LVL_BIAS[2:0] Name Type Reset SFR Address = 0xCE Name Function PA_LVL_ Number of Slices Enabled in the PA Driver. This parameter determines the output current drive of the PA. Programming this NSLICE register directly is not recommended.
  • Page 39: Xreg Definition 12.3. Bpa_Trim

    Si4010-C2 XREG Definition 12.3. bPA_TRIM PA_MAX_ Reserved Reserved Reserved Reserved Name Type Reset XREG Address = 0x4012 Name Function Unused PA MAX Drive Bit. PA_MAX_ This parameter boost the bias current of the PA by 1.5 times up to 10.5 mA. The values entered into this register come from the Power Amplifier Module API.
  • Page 40: Output Data Serializer (Ods)

    Si4010-C2 13. Output Data Serializer (ODS) 13.1. Description The ODS block is responsible for synchronizing the output data to the required data rate and maintaining a steady data flow during transmission. The serializer accomplishes the following functions: Controls the edge rate of the PA on/off transitions.
  • Page 41: Register Description

    Si4010-C2 13.3. Register Description SFR Definition 13.1. ODS_CTRL ODS_SHIFT_CTRL FSK_FOR FSK_ FORCE_ FORCE_ FORCE_ ODS_EN Name CE_DEV [1:0] MODE Type Reset SFR Address = 0xA9 Name Function ODS Output Control on Last Bit. Controls behavior of serializer when data runs out.
  • Page 42: Sfr Definition 13.2. Ods_Timing

    Si4010-C2 SFR Definition 13.2. ODS_TIMING ODS_GROUP_WIDTH[2:0] ODS_EDGE_TIME ODS_CK_DIV[2:0] Name [1:0] Type Reset SFR Address = 0xAA Name Function Controls Symbol Group width, from 2–8 Symbols. Set to 4 to transmit 5 symbol groups obtained from 4/5 encoding. Or set to 7 to send ODS_ 8 symbol group obtained from Manchester encoding of 4 bits.
  • Page 43: Sfr Definition 13.3. Ods_Data

    Si4010-C2 SFR Definition 13.3. ODS_DATA ODS_DATA[7:0] Name Type Reset SFR Address = 0xAB Name Function ODS Input Data. Symbol group register. Side effect of writing is clearing of ODS_EMPTY flag. It gener- ODS_DATA ates a single pulse for the ODS to notify the Tx ODS data SFR holding register been [7:0] written to and contains new data.
  • Page 44: Sfr Definition 13.5. Ods_Rateh

    Si4010-C2 SFR Definition 13.5. ODS_RATEH Name Reserved ODS_RATEH[6:0] Type Reset SFR Address = 0xAD Name Function Reserved Read as 0. Write has no effect. ODS_ Upper Bits of 15-bit ODS Data Rate Field. RATEH See the ODS_RATEL for description of the serializer data rates.
  • Page 45: Sfr Definition 13.7. Ods_Warm2

    Si4010-C2 SFR Definition 13.7. ODS_WARM2 Reserved ODS_WARM_LC[3:0] Name Type Reset SFR Address = 0xAF Name Function Reserved Read as 0x0. Write has no effect. Sets Warm-Up Time for the LCOSC. Sets the "warm up" interval for the LC oscillator, where it is biased up prior to ...
  • Page 46: Lc Oscillator (Lcosc)

    The technology behind the VCO is based on the Silicon Laboratories Si500 crystal-less oscillator chip and forms the core of the Si4010s' crystal-less operation. After this device is factory trimmed, the VCO fre- quency is the most accurate frequency on the chip and sets the chips transmit frequency stability unless an external crystal oscillator is used.
  • Page 47: Low Power Oscillator And System Clock Generator

    Si4010-C2 15. Low Power Oscillator and System Clock Generator The source of all digital system clocks is derived from the low power oscillator (LPOSC) and system clock generator. The LPOSC produces a 24 MHz clock signal and is used by the system clock generator to pro- duce the system clock.
  • Page 48: Sfr Definition 15.2. Sysgen

    Si4010-C2 SFR Definition 15.2. SYSGEN Name SYSGEN_ Re-served PWR_1ST RTC_ PORT_ SYSGEN_DIV[2:0] SHUT- _TIME TICKCLR HOLD DOWN Type — Reset SFR Address = 0xBE Name Function System General Shutdown. Setting this bit causes shutdown of MCU and most analog. Recovery from this is via ...
  • Page 49: Crystal Oscillator (Xo)

    Si4010-C2 16. Crystal Oscillator (XO) The crystal oscillator produces an accurate clock reference for applications demanding a high-accuracy transmit carrier frequency. It uses a 1-pin crystal oscillator circuit (Colpitt's oscillator) and the output is con- nected to the frequency counter. When crystal is used, the accuracy of the radio center frequency is deter- mined by the parameters of the crystal (such as load capacitance, crystal accuracy, etc.) and the parasitic...
  • Page 50: Frequency Counter

    Si4010-C2 17. Frequency Counter The frequency counter allows the measurement of the ratio of two selected clock sources: a low frequency clock which defines a counting interval, and a high frequency clock which is counted. The frequency counter consists of an interval counter, driven by one of the six clock sources. Programming of the interval counter determines how long the main counter will count one of the two high speed clocks, LC oscillator or DIVIDER output.
  • Page 51 Si4010-C2 When the interval counter is finished with the interval count, it clears the FC_BUSY=0 bit and after a few cycles of clk_sys synchronization delay it sets the FC_DONE=1 bit. Both interval counter and main FC_COUNT counter are stopped and the main FC_COUNT keeps the accumulated value until the fre- quency counter is disabled or triggered again.
  • Page 52: Register Description

    Si4010-C2 17.1. Register Description SFR Definition 17.1. FC_CTRL Name FC_DONE FC_BUSY FC_DIV_ Reserved FC_MODE[2:0] Type Reset SFR Address = 0x9B Name Function Frequency Counter Done. Counting done, interrupt generation level signal. Must be cleared by software ISR. It is also cleared if 1 is written to fc_busy, which denotes the start of the next count. Any FC_DONE value can be written here, so one can invoke interrupt just writing 1 here.
  • Page 53: Sfr Definition 17.2. Fc_Interval

    Si4010-C2 SFR Definition 17.2. FC_INTERVAL Name Reserved Reserved FC_INTERVAL[5:0] Type Reset SFR Address = 0x9D Name Function Reserved Reserved. Frequency Counter Interval. Controls number of interval clock cycles in an interval. INTERVAL n_cycles = (2+fcnt_interval[0])*(2^fcnt_interval[5:1]) [5:0] Note that fcnt_interval is allowed to take on values no higher than 43. If the number higher than 43 is used then the the interval counted is forced to n_cycles = 1.
  • Page 54: Sleep Timer

    Si4010-C2 18. Sleep Timer The Si4010 includes a very low-power sleep timer that can be used to support the transmit duty cycle requirements of the ETSI specification or self-wakeup for button independent applications. It consist of a low speed (~2.1 kHz), very low power oscillator with a 24 bit down counter. When programmed to its maxi- mum interval it takes ~2.1 hours to count down to zero.
  • Page 55: Microcontroller

    Si4010-C2 22. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 also includes on-chip debug hardware, and interfaces directly with the analog and digital subsystems pro- viding a complete RF transmitter solution in a single integrated circuit.
  • Page 56: Instruction Set

    Si4010-C2 With the CIP-51's maximum system clock at 24 MHz, it has a peak throughput of 24 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions in the function of the required clock cycles.
  • Page 57: Table 22.1. Cip-51 Instruction Set Summary

    Si4010-C2 Table 22.1. CIP-51 Instruction Set Summary Mnemonic Description Bytes Clock Cycles Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data...
  • Page 58 Si4010-C2 Table 22.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A RL A Rotate A left RLC A Rotate A left through Carry...
  • Page 59 Si4010-C2 Table 22.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit...
  • Page 60 Si4010-C2 Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps.
  • Page 61: Register Descriptions

    Si4010-C2 22.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to implement new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state.
  • Page 62: Sfr Definition 22.3. Sp

    Si4010-C2 SFR Definition 22.3. SP SP[7:0] Name Type Reset SFR Address = 0x81 Name Function Stack Pointer. SP[7:0] The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset.
  • Page 63: Sfr Definition 22.5. B

    Si4010-C2 SFR Definition 22.5. B B[7:0] Name Type Reset SFR Address = 0xF0; Bit-Addressable Name Function B Register. B[7:0] This register serves as a second accumulator for certain arithmetic operations. Rev. 1.0...
  • Page 64: Sfr Definition 22.6. Psw

    Si4010-C2 SFR Definition 22.6. PSW RS[1:0] PARITY Name Type Reset SFR Address = 0xD0; Bit-Addressable Name Function Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor- row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
  • Page 65: Memory Organization

    Si4010-C2 23. Memory Organization The memory organization of the Si4010 is similar to that of a standard 8051. There are two separate mem- ory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. However, this device is unique since it has the pro- gram and data memory spaces combined into one.
  • Page 66: Program Memory

    Si4010-C2 23.1. Program Memory Program memory consists of 4.5 kB for RAM and 12 kB of ROM. The device employs a unified CODE/XDATA RAM memory. On 8051 architecture the external data memory (XDATA) space is physically different from the program memory (CODE); they can be accessed with different instructions. On this device the RAM can store both CODE and XDATA at any location.
  • Page 67: Bit Addressable Locations

    Si4010-C2 23.5. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F.
  • Page 68: Mtp (Eeprom) Memory

    Si4010-C2 The maximum number of read operations of the NVM memory is limited, but this limitation has effect only in extreme conditions. Consult the electrical specification section in this document, and with “ANxxx NVM Reliability Analysis.” 23.10. MTP (EEPROM) Memory The MTP memory is a special block not organized as a usual memory.
  • Page 69: System Boot And Nvm Programming

    Si4010-C2 24. System Boot and NVM Programming The device does not include a Flash memory for permanent code or data storage. Instead, the device con- tains 4. 5kB of RAM, which can serve as a unified CODE and XDATA RAM memory. The device contains 8 kB of NVM (OTP) memory for user code and data storage.
  • Page 70: Reset

    Si4010-C2 24.2. Reset Reset circuitry allows the controller to be easily placed in a predefined default condition. See “Reset Sources” on page 106 for details. 24.3. Chip Program Levels The boot process starts by reading the NVM configuration bytes in the Factory region of NVM. The infor- mation about the programmed level of the chip is read first and the boot process acts accordingly.
  • Page 71: Nvm Organization

    Si4010-C2 24.4. NVM Organization The 8 kB NVM (OTP) memory is virtually mapped to the device address space 0xE000 .. 0xFFFF. How- ever, CPU can access NVM only indirectly using the predefined API calls in ROM. The NVM address region is organized in the following fashion: 1.
  • Page 72: Device Boot Process

    Si4010-C2 NVM 8KB 0xE000 Factory Set by the Setup factory setup wBoot_NvmUserBeg User (Boot) wBoot_NvmCopyAddr Optional gap First unread NVM byte address .. User/Run part User App (App Use) Optional 0xFFC0 Reserved 64 bytes 0xFFFF Figure 24.1. NVM Address Map 24.5.
  • Page 73: Error Handling During Boot

    Si4010-C2 cannot be cleared. When this bit is 1, then after the Factory and User loads are loaded from NVM the boot loader enables C2 and runs the user code immediately, without any wait, by executing long jump to RAM address 0x0000. The IDE can still halt the chip and connect to it in a usual fashion.
  • Page 74 Si4010-C2 The user code or user development environment need to pay attention to the content of the following vari- ables. All are stored in big endian fashion (MSB at the lower address): wBoot_DpramTrimBeg .. this variable points to the first occupied (by factory data) address of RAM.
  • Page 75: Figure 24.2. Code/Xdata Ram Address Map

    Si4010-C2 CODE/XDATA RAM 4.5KB 0x0000 User CODE/ XDATA Factory XDATA 0x11F3 wBoot_DpramTrimBeg 0x11F5 wBoot_NvmUserBeg 0x11F7 Boot_AfterTrimExe Boot_PatchExe 0x11FD wBoot_NvmCopyAddr 0x11FF bBoot_BootStat Figure 24.2. CODE/XDATA RAM Address Map Rev. 1.0...
  • Page 76: Boot Status Variables

    Si4010-C2 24.8. Boot Status Variables End of the CODE/XDATA RAM are reserved for boot status variables. The user must pay attention to the content of the wBoot_DpramTrimBeg variable. Its content points to the first reserved address for Factory Silicon Labs use.
  • Page 77 Si4010-C2 XDATA Variable Definition 24.1. bBoot_BootStat BS_GPIO_ RESERVED BS_ERR_FACTORY[2:0] BS_ERR_ BS_ERR_ Name XTAL USER_ USER_ NEXT FIRST Type Reset XDATA Address = 0x11FF Name Function GPIO0 Read before Boot. BS_GPIO_ Read GPIO0 value at the very beginning of the boot prior to optionally turning on the XO XTAL (crystal oscillator).
  • Page 78: Sfr Definition 24.2. Boot_Flags

    Si4010-C2 SFR Definition 24.2. BOOT_FLAGS Reserved Reserved BOOT_ CODE_ Reserved BOOT_ BOOT_ CODE_ Name TRIM_ RUN_ FAIL_ DONE_ RUN_SYS Type Reset SFR Address = 0xDD Name Function Reserved Reserved. Force User Part to Act as a Factory Part. For User part only: During the boot process load only Factory values and stop. By other BOOT_TRI words, act like a Factory part.
  • Page 79: Boot Routine Destination Address Space

    Si4010-C2 24.9. Boot Routine Destination Address Space The boot process reads the formatted data from NVM and writes it to the desired destination. The format supports different address regions based on the destination (write) address. The destination address is part of the NVM content data frame format.
  • Page 80: Nvm Programming

    Si4010-C2 Note that by using the unified CODE/XDATA memory and by mapping the IRAM to the boot process address space the user can initialize both XDATA and IRAM variables directly from the User NVM load without the need for running any startup code to do variable initializations, resulting in the saving of a code size.
  • Page 81: Retest And Retest Configuration

    Si4010-C2 24.11. Retest and Retest Configuration When the part is programmed as a Run part, the C2 interface is disabled and nobody can access the part externally. However, Silicon Labs needs to be able to retest the part in case it returns as a failed part from a customer application.
  • Page 82 Si4010-C2 Table 24.2. Run Chip Retest Protection Flags: NVM Programmer Flag Name Description mtp_c2_prot Protect MTP. When set then both Wr and Rd access to MTP is disabled. Forces boot process to set MTP_PROT=1 to disable MTP communication completely. Reading from MTP returns 0x00 values, writing is not possible.
  • Page 83: Boot And Retest Protection Nvm Control Byte

    Si4010-C2 24.12. Boot and Retest Protection NVM Control Byte The boot process monitors the value of an NVM byte called PROT3_CTRL. There is not a corresponding hardware register to this byte. It is a value in the Factory region at the beginning of NVM. The register contains Retest protection flags described above and modification of the boot for User part.
  • Page 84: Chip Protection Control Register

    Si4010-C2 24.13. Chip Protection Control Register The boot process sets the value of the device protection and configuration SFR register, PROT0_CTRL. The user can read the register and check the programming level of the device as well as protections set to control access to the NVM and MTP memories and C2 interface.
  • Page 85: On-Chip Registers

    The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as imple- menting additional SFRs used to configure and access the sub-systems unique to the Si4010-C2. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set.
  • Page 86: Table 25.2. Special Function Registers

    Si4010-C2 Table 25.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xE0 Accumulator 0xF0 B Register 0xDD Boot Flags BOOT_FLAGS 0x8F Clock Output Settings CLKOUT_SET 0x83 Data Pointer High...
  • Page 87 Si4010-C2 Table 25.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xB7 Port Interrupt Configuration PORT_INTCFG 0xB6 Port Set PORT_SET 0xDA Protection 0 Control PROT0_CTRL 0xD0 Program Status Word...
  • Page 88: Xreg Registers

    Si4010-C2 25.2. XREG Registers The chip contains another set of registers implemented in the XREG memory area. These registers are located in the XDATA address space, addressable by MOVX instructions only. From CPU perspective it is a regular external memory.
  • Page 89: Table 25.3. Xreg Register Memory Map In External Memory

    Si4010-C2 Table 25.3. XREG Register Memory Map in External Memory XDATA Address Type Name Byte Order 0x4002 BYTE bLPOSC_TRIM 0x4003 <reserved> 0x4007 0x4008 LWORD IFC_COUNT MSB Byte 0x4009 0x400a 0x400b LSB Byte MSB Byte 0x400c WORD wPA_CAP LSB Byte 0x400d 0x400e <reserved>...
  • Page 90: Table 25.4. Xreg Registers

    Si4010-C2 Table 25.4. XREG Registers XREGs are listed in alphabetical order. Register Address Description Page 0x4008 Frequency Counter Output lFC_COUNT 0x4002 Low Power Oscillator Trim bLPOSC_TRIM 0X4040 MTP_Read Data Bytes abMTP_RDATA[16] 0x400C PA Variable Capacitor wPA_CAP 0x4012 PA MAX Drive bit...
  • Page 91: Interrupts

    Si4010-C2 26. Interrupts The Si4010 device includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt- pending flag is set to logic ‘1’.
  • Page 92: Mcu Interrupt Sources And Vectors

    Si4010-C2 26.1. MCU Interrupt Sources and Vectors The device supports 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend- ing flag to logic ‘1’. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag.
  • Page 93: Interrupt Register Descriptions

    Si4010-C2 Table 26.1. Interrupt Summary Interrupt Source Interrupt Priority Pending Flag Enable Flag Priority Vector Order Control Reset 0x0000 None Always Always Enabled Highest External INT 0 (INT0) 0x0003 INT0_FLAG EINT0 (IE.0) PINT0 (IP.0) (INT_FLAGS.0) Timer 2 Overflow 0x000B TMR2INTL...
  • Page 94: Sfr Definition 26.1. Ie

    Si4010-C2 SFR Definition 26.1. IE EINT1 ETMR3 EODS ERTC EDMD ETMR2 EINT0 Name Type Reset SFR Address = 0xA8; Bit-Addressable Name Function Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources.
  • Page 95: Sfr Definition 26.2. Ip

    Si4010-C2 SFR Definition 26.2. IP Name Reserved PINT1 PTMR3 PODS PRTC PDMD PTMR2 PINT0 Type Reset SFR Address = 0xB8; Bit-Addressable Name Function Reserved Read = 1, Write = Don't Care. External Edge Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt.
  • Page 96: Sfr Definition 26.3. Eie1

    Si4010-C2 SFR Definition 26.3. EIE1 Name Reserved Reserved Reserved EVOID1 EVOID0 Reserved Reserved Type Reset SFR Address = 0xE6 Name Function Reserved Read as 0x0. Write has no effect. Enable VOID1 Interrupt (Reserved). This bit sets the VOID1 interrupt.(Reserved) EVOID1 0: Disable VOID1 interrupts.
  • Page 97: Sfr Definition 26.4. Eip1

    Si4010-C2 SFR Definition 26.4. EIP1 Reserved PVOID1 PVOID0 Reserved Name Type Reset SFR Address = 0xF6 Name Function Reserved Read as 0x0. Write has no effect. VOID1 Interrupt Priority Control. This bit sets the priority of the VOID1 interrupt. PVOID1 0: VOID1 interrupt set to low priority level.
  • Page 98: Sfr Definition 26.5. Int_Flags

    Si4010-C2 SFR Definition 26.5. INT_FLAGS Name Reserved Reserved Reserved VOID1_ VOID0_ ODS_ INT1_ INT0_ FLAG FLAG FLAG FLAG FLAG Type Reset SFR Address = 0xBF Name Function Reserved Read as 0x0. Write has no effect. VOID1_ Spare Interrupt Flag (can be used freely by the user application software).
  • Page 99: External Interrupts

    Si4010-C2 26.5. External Interrupts The INT0 and INT1 external interrupt sources are configurable as active high or low. They are edge sensi- tive only, not level sensitive. These are not the same INT0 and INT1 as found on original 8051 architecture.
  • Page 100: Sfr Definition 26.6. Port_Intcfg

    Si4010-C2 SFR Definition 26.6. PORT_INTCFG NEG_ SEL_INT1[2:0] NEG_ SEL_INT0[2:0] Name INT1 INT0 Type Reset SFR Address = 0xB7 Name Function Negative INT1 Polarity. This bit selects whether the selected INT1 GPIO input will get inverted or pass as is NEG_ before going to the edge detector.
  • Page 101: Power Management Modes

    Si4010-C2 27. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers are inactive. The system clock is still running when the CPU is in Stop mode.
  • Page 102: Sfr Definition 27.1. Pcon

    Si4010-C2 SFR Definition 27.1. PCON GF[5:0] STOP IDLE Name Type Reset SFR Address = 0x87 Name Function General Purpose Flags 5–0. GF[5:0] These are general purpose flags for use under software control. Stop Mode Select. STOP Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
  • Page 103: Aes Hardware Accelerator

    Si4010-C2 28. AES Hardware Accelerator The device implements the AES (Advanced Encryption Standard) hardware accelerator. It is not a full hardware solution. The hardware accelerator is used by the Silicon Labs API firmware to implement AES 128 bit encrypt/decrypt functions. If the user wants to implement proprietary AES implementation in firm- ware it is possible to use the AES hardware accelerator.
  • Page 104: Sfr Definition 28.1. Gfm_Data

    Si4010-C2 SFR Definition 28.1. GFM_DATA GFM_DATA[7:0] Name Type Reset SFR Address = 0x84 Name Function GFM Multiplier Data Processing. Writing of a value here registers the data for processing. Processed data is regis- GFM_DATA tered into the same register with single CLK_SYS cycle delay. Read from this reg- [7:0] ister reads the processed multiplied data.
  • Page 105: Sfr Definition 28.3. Sbox_Data

    Si4010-C2 SFR Definition 28.3. SBOX_DATA SBOX_DATA[7:0] Name Type Reset SFR Address = 0x86 Name Function AES SBox Processing. Writing of a value here registers the data for processing. Processed data is regis- SBOX_DATA tered into the same register with single CLK_SYS cycle delay. Read from this reg- [7:0] ister reads the processed data.
  • Page 106: Reset Sources

    Si4010-C2 29. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. There is only one external reset source for the device, which is power on reset. It gets invoked at two occasions: 1. Power is supplied to the device. This means connecting the power supply to disconnected device or cycling the external power to the device.
  • Page 107: Software Reset

    Si4010-C2 29.3. Software Reset There is no traditional software reset on the Si4010, but a similar result can be achieved by setting up the sleep timer and then putting the device into shutdown mode. This action effective disconnects power to the internal systems of the device.
  • Page 108: Port Input/Output

    Si4010-C2 30. Port Input/Output Digital resources are available through up to 10 I/O pins. The number of I/O depends on the package: 10 pin package .. 6 port pins organized as 6 bottom bits of Port 0.  14 pin package .. 10 port pins organized as a full 8-bit Port 0 and 2 bottom bits of Port 1....
  • Page 109: Table 30.1. 10-Pin Mode

    Si4010-C2 Pin assignments for 10– and 14–pin packages are shown in Table 30.1 and Table 30.2. Table 30.1. 10–Pin Mode Package Pin Package Pin Number Name GPIO0/XO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5/LED Table 30.2. 14–Pin Mode Package Pin Package Pin...
  • Page 110: Figure 30.2. Gpio[3:1] Functional Diagram

    Si4010-C2 Digital logic GPIO Pads Wr: PORT_MATRIX Wr: PORT_ROFF PORT_STROBE Rd: PORT_MATRIX Rd: PORT_ROFF gpio_in[n] gpio_push_pull[n] port_push_pull[n] ~50k port_oe[n] gpio_dataout[n] GPIO[n] port_dataout[n] Figure 30.2. GPIO[3:1] Functional Diagram Functional diagram of the other GPIO ports is in Figure 30.3. It is the general GPIO circuit that can be forced by digital control to have limited functionality (e.g., as input only, etc.).
  • Page 111: Gpio Pin Special Roles

    Si4010-C2 30.1. GPIO Pin Special Roles Not all GPIO ports can be configured as both input and outputs. Given the limited number of GPIO each pin can assume different functionality based on the software configuration of the ports. The functionality of each GPIO is described in Table 30.3.
  • Page 112: Pullup Roff Option

    Si4010-C2 30.2. Pullup Roff Option There is an option to disable the weak pullup pad resistors. This feature is called Roff option. The Roff option is controlled directly by the GPIO pads and persist when the chip is in the shutdown mode. Control of the Roff control bit in the GPIO is described in section 30.4.
  • Page 113: Figure 30.4. Push Button Organization In Matrix Mode

    Si4010-C2 GPIO[9] GPIO[8] 14 pin package only GPIO[7] GPIO[6] GPIO[0] GPIO[4] Pushbuttons connecting the crossing wires: Wr: PORT_MATRIX PORT_STROBE GPIO[3] GPIO[2] GPIO[1] Figure 30.4. Push Button Organization in Matrix Mode Rev. 1.0...
  • Page 114: Pullup Roff And Matrix Mode Option Control

    Si4010-C2 30.4. Pullup Roff and Matrix Mode Option Control Both Roff and Matrix mode options are controlled by the GPIO pad itself. The control is implemented as 2 bit latch inside of the GPIO pads. Both options stay in their used defined states during chip shutdown. In other words, if the chip is in shutdown mode, the digital logic does not have power, but the two GPIO latches keep the user set values of those options.
  • Page 115: Special Gpio Modes Control

    Si4010-C2 In assembly: orl P0, #00001110B ; Turn GPIO[3:1] as inputs anl P0CON, #NOT 00001110B anl PORT_CTRL, #NOT(M_PORT_MATRIX OR M_PORT_ROFF) orl PORT_CTRL, #M_PORT_MATRIX ; Set Matrix mode and keep resistors orl PORT_CTRL, #M_PORT_STROBE ; Strobe new Matrix/Roff modes to GPIO anl PORT_CTRL, #NOT(M_PORT_STROBE) 30.5.
  • Page 116: Table 30.4. Gpio Special Roles Control And Order

    Si4010-C2 Table 30.4. GPIO Special Roles Control and Order GPIO Roles Order Control Comment NVM programming voltage VPP = 6.5 V XO_CTRL.XO_ENA GPIO P0.0 fixed as input only GPIO P0.1 P0CON.1 Matrix, Roff Ind* PORT_CTRL GPIO P0.2 P0CON.2 Matrix, Roff Ind* PORT_CTRL...
  • Page 117: Led Driver On Gpio[5]

    Si4010-C2 30.6. LED Driver on GPIO[5] For application mode the GPIO[5] is shared with LED current driver. The LED current driver provides three levels of LED current, 1mA maximum. The current levels are described in SFR Definition 30.6. User can set the current intensity and then control the LED on and off by P0.5, port P0 bit 5, as a regular output.
  • Page 118: Sfr Definition 30.1. P0

    Si4010-C2 SFR Definition 30.1. P0 P0[7:0] Name Type Reset SFR Address = 0x80 Name Function Port 0 Register, GPIO[7:0], Bit Addressable. Write appears at the GPIO[7:0] outputs, read reads directly the GPIO input values. Write: 0 .. output low value 1 ..
  • Page 119: Sfr Definition 30.2. P0Con

    Si4010-C2 SFR Definition 30.2. P0CON P0CON[7:0] Name Type Reset SFR Address = 0xA4 Name Function Port 0 Configuration Register, for GPIO[7:0]. This bit controls configuration of each corresponding output bit in P0. 0 .. open-drain 7:0 P0CON[7:0] 1 .. push-pull If the pin to be input, it must be configured as open-drain and 1 has to be written as output value to it.
  • Page 120: Sfr Definition 30.4. P1Con

    Si4010-C2 SFR Definition 30.4. P1CON P1CON[7:0] Name Type Reset SFR Address = 0xA5 Name Function Port 1 Register GPIO[15:8], Bit Addressable. This bit controls configuration of each corresponding output bit in P1. 0 .. open-drain, pull up resistor connected (see PORT_ROFF) 7:0 P1CON[7:0] 1 ..
  • Page 121: Sfr Definition 30.6. Port_Ctrl

    Si4010-C2 SFR Definition 30.6. PORT_CTRL PORT_ PORT_ PORT_ PORT_ PORT_5_ PORT_ PORT_LED[1:0] Name MATRIX STROBE ROFF DRV2X MID- MID- RANGE RANGE Type — — Reset SFR Address = 0xB5 Name Function Port Strobe. Strobe the port_matrix and port_roff bits values from this register to the GPIO pads.
  • Page 122: Sfr Definition 30.7. Port_Set

    Si4010-C2 SFR Definition 30.7. PORT_SET EDGE_ EDGE_ PORT_CLKOUT[1:0] PORT_ PORT_ Reserved Reserved Name INT1 INT0 CLKEN REFEN Type Reset SFR Address = 0xB6 Name Function Edge Control for INT1. EDGE_ This bit controls whether single edge or both edges invoke the interrupt.
  • Page 123: Clock Output Generation

    Si4010-C2 31. Clock Output Generation The device includes an option to be used as a clock generator for other chips connected to the device. The generated clock frequency, clk_out, is derived from the internal 24MHz oscillator. System clock division set in SYSGEN register has no effect on the clk_out frequency.
  • Page 124: Register Description

    Si4010-C2 31.1. Register Description SFR Definition 31.1. CLKOUT_SET Name CLKOUT_ CLKOUT_ CLKOUT_ CLKOUT_DIV[4:0] Type Reset SFR Address = 0x8F Name Function CLKOUT Clear. Write 1 to this bit clears the generated clock divider. The generated clock output is forced to 0.
  • Page 125 Si4010-C2 Name Function CLKOUT Symmetry. If this bit set to 1 then the output clock duty cycle is very close to 1:1 irrespective of the division factor. However, the generated clock waveform is a combination of CLKOUT_ outputs of two flops and therefore might jitter more. If this bit is 0 then for odd division factor there is a single 24 MHz period difference in between halves of the generation output clock.
  • Page 126: Control And System Setting Registers

    Si4010-C2 32. Control and System Setting Registers The following are general system setting control registers as well as general purpose scratch pad regis- ters. GPR_CTRL and GPR_DATA can be used as a general purpose 2 byte SFR register. They do not con- trol any hardware on the device.
  • Page 127: Sfr Definition 32.3. Rbit_Data

    Si4010-C2 SFR Definition 32.3. RBIT_DATA Name Reserved Reserved GPIO_ ODS_ ODS_NOD Reserved Reserved LED_ CKGOOD EMPTY DRIVE Type Reset SFR Address = 0x99 Name Function Reserved Read as 0x0. Write has no effect. GPIO LED Drive. Actual status of the LED drive. If this bit is at 1, then the LED driver is GPIO_LED_DRIVE actually on.
  • Page 128: Real Time Clock Timer

    Si4010-C2 33. Real Time Clock Timer The Si4010 device contains a real time clock (RTC) timer. This dedicated timer provides accurate interrupt request pulses in precise time intervals. The device does not contain any hardware nor any battery backed up real time clock. The purpose of RTC timer is to provide accurate time intervals for user application at run time, not an absolute real calendar time.
  • Page 129: Rtc Interrupt Flag Time Uniformity

    Si4010-C2 33.1. RTC Interrupt Flag Time Uniformity Since 100 µs and 200 µs pulse duration is not exactly an integer multiple of the 24 MHz/128 frequency, the fractional division was used. The 100 µs and 200 µs pulse durations are uniform on average, when observed over a sufficiently long timer period.
  • Page 130: Sfr Definition 33.1. Rtc_Ctrl

    Si4010-C2 SFR Definition 33.1. RTC_CTRL Name RTC_INT RTC_ENA RTC_CLR Reserved Reserved RTC_DIV[2:0] Type Reset SFR Address = 0x9C Name Function Real Time Clock Interrupt Flag. RTC_INT Set after the time interval set by RTC_DIV field elapses. Software must clear the flag.
  • Page 131: Timers 2 And 3

    Si4010-C2 34. Timers 2 and 3 The Si4010 device includes two identical timers, Timer 2 (TMR2) and Timer 3 (TMR3). Since the timers are identical, the description will refer to Timer 2 (TMR2). The reader can replace the TMR2 with TMR3 in the text to get the description of Timer 3 (TMR3).
  • Page 132: Interrupt Flag Generation

    Si4010-C2 34.1. Interrupt Flag Generation Timer 2 has a single interrupt signal going to interrupt controller. Internally, there are 2 interrupt flags, TMR2INTH for high half of the timer and TMR2INTL for low half of the timer, which are combined to gener- ate the final interrupt signal.
  • Page 133: 16-Bit Timer With Auto Reload (Wide Mode)

    Si4010-C2 34.2. 16-bit Timer with Auto Reload (Wide Mode) When TMR2SPLIT=0 and TMR2L_CAP=0, the timer operates as a 16-bit timer with auto reload. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the time reload registers (TMR2RH and TMR2RL) is loaded into the timer register as shown in Figure 34.2, and the...
  • Page 134: 8-Bit Timer/Timer Mode (Split Mode)

    Si4010-C2 TMR_CLKSEL TMR2L_RUN Interrupt clk_sys TMR2INTH clk_sys/12 TMR2INTL TMR2L TMR2H rtc_tick (5.33us) TMR2INTL_EN rtc_pulse (100us) TMR2SPLIT TMR2H_CAP TMR2L_CAP Capture INT0 TMR2RL TMR2RH TMR2H_RUN INT1 for TMR3 TMR2L_RUN Figure 34.3. Capture 16-bit Mode Block Diagram (Wide Mode) 34.4. 8-Bit Timer/Timer Mode (Split Mode) When TMR2SPLIT=1, the timer operates as two independent 8-bit timers.
  • Page 135: 8-Bit Capture/Capture Mode (Split Mode)

    Si4010-C2 TMR_CLKSEL TMR2H_RUN clk_sys Interrupt clk_sys/12 TMR2INTH TMR2H rtc_tick (5.33us) TMR2INTL rtc_pulse (100us) TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2RH TMR2L_CAP Reload TMR2H_RUN TMR2L_RUN TMR2L_RUN TMR2L TMR2RL Reload Figure 34.4. Two 8-bit Timers in Timer/Timer Configuration (Split Mode) 34.5. 8-Bit Capture/Capture Mode (Split Mode) When TMR2SPLIT=1, TMR2L_CAP=1 and TMR2H_CAP=1, both halves operate independently in 8-bit capture modes.
  • Page 136: 8-Bit Timer/Capture Mode (Split Mode)

    Si4010-C2 TMR_CLKSEL TMR2H_RUN clk_sys Interrupt clk_sys/12 TMR2INTH TMR2H rtc_tick (5.33us) TMR2INTL rtc_pulse (100us) TMR2INTL_EN TMR2SPLIT TMR2H_CAP Capture TMR2RH TMR2L_CAP TMR2H_RUN TMR2L_RUN TMR2L_RUN TMR2L Capture INT0 TMR2RL INT1 for TMR3 Figure 34.5. Two 8-bit Timers in Capture/Capture Configuration (Split Mode) 34.6. 8-Bit Timer/Capture Mode (Split Mode) When TMR2SPLIT=1, TMR2L_CAP=1 and TMR2H_CAP=0, the split timers operate one in 8-bit timer mode and the other in 8-bit capture mode.
  • Page 137: Figure 34.6. Two 8-Bit Timers In Timer/Capture Configuration (Split Mode)

    Si4010-C2 TMR_CLKSEL TMR2H_RUN clk_sys Interrupt clk_sys/12 TMR2H TMR2INTH rtc_tick (5.33us) TMR2INTL rtc_pulse (100us) TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2RH TMR2L_CAP Reload TMR2H_RUN TMR2L_RUN TMR2L_RUN TMR2L Capture INT0 TMR2RL INT1 for TMR3 Figure 34.6. Two 8-Bit TImers in Timer/Capture Configuration (Split Mode) Rev. 1.0...
  • Page 138: Figure 34.7. Two 8-Bit Timers In Capture/Timer Configuration (Split Mode)

    Si4010-C2 TMR_CLKSEL TMR2H_RUN clk_sys Interrupt clk_sys/12 TMR2INTH TMR2H rtc_tick (5.33us) TMR2INTL rtc_pulse (100us) TMR2INTL_EN TMR2SPLIT TMR2H_CAP Capture TMR2RH TMR2L_CAP TMR2H_RUN TMR2L_RUN TMR2L_RUN TMR2L INT0 TMR2RL INT1 for TMR3 Reload Figure 34.7. Two 8-Bit Timers In Capture/Timer Configuration (Split Mode) Rev. 1.0...
  • Page 139: Sfr Definition 34.1. Tmr_Clksel

    Si4010-C2 SFR Definition 34.1. TMR_CLKSEL TMR3H_MODE TMR3L_MODE TMR2H_MODE TMR2L_MODE Name Type Reset SFR Address = 0xC9 Name Function Timer 3 High Byte Mode Select. Timer 3 high half in split mode. Ignored if Timer 3 is in wide mode. TMR3H_...
  • Page 140: Sfr Definition 34.2. Tmr2Ctrl

    Si4010-C2 SFR Definition 34.2. TMR2CTRL TMR2 TMR2 TMR2 TMR2 TMR2H_ TMR2L_ TMR2H_ TMR2L_ Name INTH INTL INTL_EN SPLIT Type Reset SFR Address = 0xC8; Bit-Addressable Name Function Timer 2 High Byte Interrupt Flag. TMR2 Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide INTH configuration.
  • Page 141 Si4010-C2 Name Function Timer 2 High Byte Run Model. TMR2H_ TMR2H high byte enable in split configuration. Ignored if timer operates in wide con- figuration. Timer 2 Low Byte Run Model. TMR2L_ TMR2L low byte enable in split configuration, whole timer enable in wide configura- tion.
  • Page 142: Sfr Definition 34.3. Tmr2Rl

    Si4010-C2 SFR Definition 34.3. TMR2RL TMR2RL[7:0] Name Type Reset SFR Address = 0xCA Name Function Timer 2 Capture/Reload Register Low Byte. TMR2RL holds the low byte of the capture/reload value for Timer 2. LSB Byte. Two halves are not double buffered. Write to each of the halves takes effect immedi- TMR2RL[7:0] ately.
  • Page 143: Sfr Definition 34.5. Tmr2L

    Si4010-C2 SFR Definition 34.5. TMR2L TMR2L[7:0] Name Type Reset SFR Address = 0xCC Name Function Timer 2 Low Byte Actual Timer Value. TMR2L[7:0] In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8- bit mode, TMR2L contains the 8-bit low byte timer value.
  • Page 144: Sfr Definition 34.7. Tmr3Ctrl

    Si4010-C2 SFR Definition 34.7. TMR3CTRL TMR3 TMR3 TMR3 TMR3 TMR3H_ TMR3L_ TMR3H_ TMR3L_ Name INTH INTL INTL_EN SPLIT Type Reset SFR Address = 0xB9 Name Function Timer 3 High Byte Interrupt Flag. TMR3 Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide INTH configuration.
  • Page 145 Si4010-C2 Name Function Timer 3 High Byte Run Model. TMR3H_ TMR3H high byte enable in split configuration, whole timer enable in wide configura- tion. Timer 3 Low Byte Run Model. TMR3L_ TMR3L low byte enable in split configuration, whole timer enable in wide configura- tion.
  • Page 146: Sfr Definition 34.8. Tmr3Rl

    Si4010-C2 SFR Definition 34.8. TMR3RL TMR3RL[7:0] Name Type Reset SFR Address = 0xBA Name Function Timer 3 Capture/Reload Register Low Byte. TMR3RL holds the low byte of the capture/reload value for Timer 3. LSB Byte. Two halves are not double buffered. Write to each of the halves takes effect immedi- TMR3RL[7:0] ately.
  • Page 147: Sfr Definition 34.10. Tmr3L

    Si4010-C2 SFR Definition 34.10. TMR3L TMR3L[7:0] Name Type Reset SFR Address = 0xBC Name Function Timer 3 Low Byte Actual Timer Value. TMR3L[7:0] In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8- bit mode, TMR3L contains the 8-bit low byte timer value.
  • Page 148: C2 Interface

    Si4010-C2 35. C2 Interface The devices include an on-chip Silicon Laboratories 2-Wire (C2) debug interface in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CLK) and a bi- directional C2 data signal (C2DAT) to transfer information between the device and a host system. The C2 interface is intended to be used by the Silicon Labs or third party development tools.
  • Page 149 Si4010-C2 On this device the GPIO[5] is shared with the LED current driver, which can drive up to 1mA of current to the ground. Normally the LED will be connected in between the GPIO[5] and VDD. For C2 to work the LED driver is disabled during debugging sessions, so even if the user code tries to turn the LED on, that opera- tion will not interfere with C2 debug transactions and the actual LED current driver will not be turned on.
  • Page 150: Figure 35.2. 14-Pin C2 Toolstick Connection To Device

    Si4010-C2 If pushbutton on keyfob development board, then it has to be isolated by R5 SW_GPIO4 GPIO4 C2DAT Device For debugging chain to work, LED must be isolated by R6 GPIO5 C2CLK 1mA max ToolStick PCB edge connector Can be used directly as local VDD VDO (+3.3V/200mA)
  • Page 151: Ide Development Environment And Debugging Chain

    Si4010-C2 36. IDE Development Environment and Debugging Chain The development platform will be provided by Silicon Labs. The debugging chain consists of an evaluation board or an evaluation keyfob, USB debug adapter or a USB based ToolStick, and the Silicon Labs IDE development environment.
  • Page 152: Chip Shutdown Limitation

    Si4010-C2 36.2. Chip Shutdown Limitation While developing firmware on an unprogrammed chip the user cannot call the API function vSys_Shutdown() to shutdown the chip without loosing the RAM code downloaded by IDE. Instead, the user should comment out the call to the shutdown function and replace it with a temporary code, which monitors a button press, actually monitoring P0 and P1 port inputs based on the user current port settings.
  • Page 153 Si4010-C2 For example, on the keyfob battery backed up development platform the user can disconnect the keyfob from the debugging platform (programming board or directly from the ToolSTick) and walk around with running application using LED as desired by the application. The only thing the user has to do is to Disconnect the keyfob from the IDE by pressing the Disconnect button.
  • Page 154: Additional Reference Resources

    Si4010-C2 37. Additional Reference Resources AN369: Antenna Interface for the Si401x Transmitters  AN370: Si4010 Software Programming Guide  AN511: Si4010 NVM Burner user's guide  AN515: Si4010 Key fob Development Kit Quick-Start Guide  AN518: Si4010 Memory Overlay Technique ...
  • Page 155: Document Change List

    Resources to include new application notes Revision 0.5 to Revision 0.6 Removed revision B part numbers and replaced with  revision C part numbers Si4010-C2-GT and Si4010- C2-GS Revision 0.6 to Revision 1.0 Updated electrical specifications to final values. ...
  • Page 156: Contact Information

    Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
  • Page 157 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Silicon Laboratories Si4010-B1-GS Si4010-B1-GT SI4010-B1-GS SI4010-B1-GT...

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