Sfr Definition 13.2. Ods_Timing - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 13.2. ODS_TIMING

Bit 7
ODS_GROUP_WIDTH[2:0]
Name
R/W R/W
Type
0
Reset
SFR Address = 0xAA
Bit Name
Controls Symbol Group width, from 2–8 Symbols.
Set to 4 to transmit 5 symbol groups obtained from 4/5 encoding. Or set to 7 to send
ODS_
8 symbol group obtained from Manchester encoding of 4 bits. Note that
7:5 GROUP_
ods_group_width can be changed dynamically prior to writing the ODS_DATA regis-
WIDTH[2:0]
ter, should you want to (for example) add 2 more symbols to the end of a 
transmission which was previously using 8 symbol groups.
Controls PA Edge Time.
ODS_
Additional division factor in range 1-4 (ods_edge time+1). Edge rate:
EDGE_
8 x (ods_ck_div+1)*(ods_edge_time+1)/24 MHz. When clk_ods is in range of 3-
4:3
TIME
8 MHz, edge rate can be selected from 1us to 10.7 µs. Study has indicated that in the
[1:0] worst case (20 kbps Manchester), edge rates somewhat higher than 4 µs are
needed.
Controls the Clock of the ODS.
Sets the division factor of the 24 MHz system clock to produce clk for the ODS mod-
ule.
ODS_CK_
2:0
Division factors are 1–8 (ods_ck_div+1). Generally should select factor which
DIV[2:0]
produces serializer clock in range of ~ 3-8 MHz.
Using the Si4010 calculator spreadsheet in order to determine the correct value of
this parameter is strongly recommended.
42
6 5 4
ODS_EDGE_TIME
R/W R/W
0 0 0
Rev. 1.0
3 2
ODS_CK_DIV[2:0]
[1:0]
R/W R/W
0 0
Function
1 0
R/W R/W
0 0