Chip Protection Control Register; Sfr Definition 24.4. Prot0_Ctrl - Silicon Laboratories Si4010-C2 Manual

Crystal-less soc rf transmitter
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Si4010-C2

24.13. Chip Protection Control Register

The boot process sets the value of the device protection and configuration SFR register, PROT0_CTRL.
The user can read the register and check the programming level of the device as well as protections set to
control access to the NVM and MTP memories and C2 interface. The register is user writable, but once a
value of 1 is written to any of the bits in the register it cannot be written as 0. Only cycling the power to the
part clears the bits, but the boot process will set this register again to the value stored in NVM. Protections
can only be made stronger, not weaker. Writing to this register does not affect the underlying data located
in NVM.

SFR Definition 24.4. PROT0_CTRL

Bit
7
NVM_
C2_OFF
Name
PROT
R/W
R/W
Type
0
Reset
SFR Address = 0xDA
Bit
Name
NVM_
NVM Protection.
Disable NVM access completely. Neither read nor write to NVM is possible. Write 1
7
PROT
sets the bit, write 0 has no effect.
C2 Interface Disable.
Write 1 sets the bit, write 0 has no effect. This bit is reset by the main digital power on
6
C2_OFF
reset. Power has to be cycled to reset this bit or chip has to wake up from shutdown.
If C2 is disabled then the chip is not accessible by a debug chain and not available for
retest.
5
Reserved
Reserved.
MTP Protection.
MTP_
4
Disable MTP access. If set then MTP will be completely disabled. All reads from MTP
PROT
will be 0x00. Write 1 sets the bit, write 0 has no effect.
NVM_
NVM Write Protection.
If this bit is set the NVM is write protected. However, the value is used only if the chip
WR_
3
program level is Run, NVM_BLOWN=3'b11x. In all other cases the value of this bit is
PROT
ignored.
Displays Chip Program Level.
NVM_
The bits can only be set to 1, write 0 has no effect:
BLOWN
2:0
001 .. Factory
[2:0]
011 .. User
111 .. Run
84
6
5
Reserved
MTP_
PROT
R
R/W
0
1
Rev. 1.0
4
3
2
NVM_
WR_
PROT
R/W
R/W
0
0
0
Function
1
0
NVM_BLOWN[2:0]
R/W
R/W
0
0

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