On-Chip Registers; Special Function Registers; Table 25.1. Special Function Register (Sfr) Memory Map - Silicon Laboratories Si4010-C2 Manual

25. On-Chip Registers

There are two register regions on chip:
Special Function Registers region

XREG region


25.1. Special Function Registers

The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si4010-C2's resources and peripherals.
The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as imple-
menting additional SFRs used to configure and access the sub-systems unique to the Si4010-C2. This
allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set.
Table 25.2 lists the SFRs implemented in the Si4010-C2 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, P1, ACC, IE, etc.) are bit-address-
able as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the
SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and
should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 25.2, for a
detailed description of each register.

Table 25.1. Special Function Register (SFR) Memory Map

0X80 0x90
P0* P1*
0*
SP
1
DPL
2
DPH
3
GFM_DATA
4
GFM_CONST
5
SBOX_DATA
6
PCON
7
8*
RBIT_DATA
9
A
FC_CTRL
B
RTC_CTRL
C
FC_INTERVAL ODS_RATEH
D
E
CLKOUT_SET
F
*Notes: Bit addressable registers.
0xA0 0xB0
P2*
GPR_CTRL
GPR_DATA
P0CON
P1CON PORT_CTRL
PORT_SET
PORT_INTCFG
IE* IP*
ODS_CTRL TMR3CTRL TMR_CLKSEL
ODS_TIMING TMR3RL
ODS_DATA TMR3RH
ODS_RATEL TMR3L
TMR3H
ODS_WARM1 SYSGEN
ODS_WARMS2 INT_FLAGS
Rev. 1.0
Si4010-C2
0xC0 0xD0
PSW*
TMR2CTRL*
TMR2RL PROT0_CTRL
TMR2RH
TMR2L
TMR2H BOOT_FLAGS
PA_LVL
0xE0 0xF0
ACC* B*
LC_FSK
EIE1 EIP1
SYS_SET
85