Sfr Definition 28.3. Sbox_Data; Sfr Definition 28.4. Sys_Set - Silicon Laboratories Si4010-C2 Manual

SFR Definition 28.3. SBOX_DATA

Bit 7
Name
R/W R/W
Type
0
Reset
SFR Address = 0x86
Bit Name
AES SBox Processing.
Writing of a value here registers the data for processing. Processed data is regis-
SBOX_DATA
7:0
tered into the same register with single CLK_SYS cycle delay. Read from this reg-
[7:0]
ister reads the processed data. The type of SBox processing is controlled by
AES_DECRYPT bit

SFR Definition 28.4. SYS_SET

Bit 7 6
Name Reserved Reserved Reserved Reserved AES_DECRYPT Reserved Reserved Reserved
R/W R/W
Type
0 0
Reset
SFR Address = 0xEE
Bit Name
7:5 Reserved
4 Reserved
AES_DECRYPT
Reserved
6 5 4
SBOX_DATA[7:0]
R/W R/W
0 0 0
5 4
R/W R/W
0 1
Reserved. Read as 0x0. Write has no effect.
Reserved. Do not write to this bit.
AES SBox Hardware Logic Control.
0: SBox is set for encryption.
1: SBox is set for decryption.
Reserved. Do not change these values.
Rev. 1.0
Si4010-C2
3 2
R/W R/W R/W
0 0
Function
3 2
R/W R/W
0 0
Function
1 0
R/W
0 0
1 0
R/W R/W
0 0
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