Sfr Definition 26.1. Ie - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 26.1. IE

Bit 7
EA EINT1
Name
R/W R/W
Type
0
Reset
SFR Address = 0xA8; Bit-Addressable
Bit Name
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
7 EA
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Enable External Edge Interrupt 1.
This bit sets the masking of External Interrupt 1.
6 EINT1
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
5 ETMR3
0: Disable Timer 3 interrupt.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Enable Output Data Serializer Interrupt.
This bit sets the masking of the ODS interrupt.
4 EODS
0: Disable ODS interrupt.
1: Enable ODS interrupt.
Enable Real Time Clock Interrupt.
This bit sets the masking of the RTC interrupt.
3 ERTC
0: Disable all RTC interrupt.
1: Enable RTC interrupt.
Enable DMD (TS Demodulator).
This bit sets the masking of the DMD interrupt.
2 EDMD
0: Disable DMD interrupt.
1:Enable DMD interrupt.
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
1 ETMR2
0: Disable all Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2 flag.
Enable External Edge Interrupt 0.
This bit sets the masking of External Interrupt 0.
0 EINT0
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
94
6 5 4
ETMR3 EODS
R/W R/W
0 0 0
Rev. 1.0
3 2
ERTC EDMD
R/W R/W
0 0
Function
1 0
ETMR2 EINT0
R/W R/W
0 0