Register Description; Sfr Definition 12.1. Pa_Lvl - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

12.1. Register Description

SFR Definition 12.1. PA_LVL

Bit 7
Name
Type
Reset
SFR Address = 0xCE
Bit Name
PA_LVL_
Number of Slices Enabled in the PA Driver.
This parameter determines the output current drive of the PA. Programming this
7:3 NSLICE
register directly is not recommended. Use the vPa_Setup() API function instead.
[4:0]
PA_LVL_
PA Level Bias.
This parameter determines the bias current per slice of the PA. Programming this
2:0 BIAS
register directly is not recommended. Use the vPa_Setup() API function instead.
[2:0]
XREG Definition 12.2. wPA_CAP
Byte
Offset
Name
Type
Reset
XREG Address = 0x400C
Bit Name
PA Variable Capacitance.
9-bit linear control value of the output capacitance of the PA. Accessed as 2 bytes
PA_CAP
(word) in big-endian fashion. Upper bits [15:9] are read as 0. Range: 2.4–12.5 pF (not
1:0
[1:0]
exact values). The resonance frequency and impedance matching between the PA
output and the connected antenna can be tuned by changing this value. This register
is set by the Power Amplifier Module API.
38
6 5 4
PA_LVL_NSLICE[4:0]
R/W
0
1
PA_CAP[1:0]
0x00
Rev. 1.0
3 2
PA_LVL_BIAS[2:0]
Function
R/W
0x00
Function
1 0
R/W
0
0