Sfr Definition 33.1. Rtc_Ctrl - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 33.1. RTC_CTRL

Bit 7
Name RTC_INT RTC_ENA RTC_CLR Reserved
R/W R/W
Type
0
Reset
SFR Address = 0x9C
Bit Name
Real Time Clock Interrupt Flag.
7 RTC_INT
Set after the time interval set by RTC_DIV field elapses. Software must clear the flag.
Hardware will not clear the flag
Real Time Clock Enable.
If set to 1 then the RTC_TICK and bottom part of the pulse generator starts running
6 RTC_ENA
where it left off. If RTC_DIV >=3 then top half also starts.
0: RTC disabled
1: RTC enabled.
Real Time Clock Clear.
Writing 1 will clear the pulse generator but will leave the RTC_TICK generator intact.
5 RTC_CLR
See the RTC_TICKCLR in the SYSGEN register for clearing the RTC_TICK counter.
0: Normal operation
1: RTC cleared
4:3 Reserved Read as 0x00. Write has no effect.
Real Time Clock Divider.
Select the divider of the RTC_TICK to determine the interval for the RTC interrupt
generation.
000: No interrupt generation
001: 100 µs .. it is a 19/19/19/18 divider
RTC_DIV
2:0 010: 200 µs .. it is a 38/37 divider
[2:0]
011: 400 µs
100: 800 µs
101: 1 ms
110: 2 ms
111: 5 ms
130
6 5 4
W R
0 0 0
Rev. 1.0
3 2
Reserved RTC_DIV[2:0]
R
0 0
Function
1 0
R/W
0 0