Sfr Definition 34.2. Tmr2Ctrl - Silicon Laboratories Si4010-C2 Manual

Si4010-C2

SFR Definition 34.2. TMR2CTRL

Bit 7
TMR2 TMR2
Name
INTH INTL
R/W R/W
Type
0
Reset
SFR Address = 0xC8; Bit-Addressable
Bit Name
Timer 2 High Byte Interrupt Flag.
TMR2
Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide
7
INTH
configuration. It gets set when the high half of the timer overflows or there is a cap-
ture event for the high half. This bit is not automatically cleared by hardware.
Timer 2 Low Byte Overflow Flag.
Interrupt flag for the timer low half. It gets set when the low half overflows in timer
mode or by capture event of the low half in capture mode. Software must clear this
bit, hardware will not clear it.
This bit is set when the low half of the timer overflows even if we operate in wide con-
TMR2
6
figuration.
INTL
When in wide configuration and in capture mode this bit is set when the high half of
the timer overflows. Since in that case the capture event is the same for both halves,
the capture event sets the TMR2INTH interrupt flag. Then this TMR2INTL can be
used as a flag that the timer overflew, serving as an additional 17th timer bit in cap-
ture mode in wide configuration.
Timer 2 Low Byte Interrupt Enable.
TMR2
When set to 1, this bit enables Timer 2 Low Byte interrupts. The overall timer inter-
5
INTL_EN
rupt request signal is : TMR2 interrupt request = TMR2INTH | (TMR2INTL &
TMR2INTL_EN)
Timer 2 Split Mode Enable.
TMR2
0: Timer operates in wide configuration as 16 bit timer. The low half controls the
4
SPLIT whole timer.
1: Timer operates in split configuration. Both halves are controlled independently.
Timer 2 High Byte Capture Mode Enable.
TMR2H_
3
If set then TMR2H high half operates in capture mode if the timer is in split configura-
CAP
tion mode. Ignored if the timer operates in wide configuration mode.
Timer 2 Low Byte Capture Mode Enable.
TMR2L_
2
If set then TMR2L low half operates in capture mode if the timer is in split configura-
CAP
tion, or the whole timer operates in capture mode if in wide configuration mode.
140
6 5 4
TMR2 TMR2
INTL_EN SPLIT
R/W R/W
0 0 0
Rev. 1.0
3 2
TMR2H_ TMR2L_ TMR2H_
CAP CAP
R/W R/W
0 0
Function
1 0
TMR2L_
RUN RUN
R/W R/W
0 0