Silicon Laboratories Si4010-GT Manuals

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Silicon Laboratories Si4010-GT Manual (157 pages)

CRYSTAL-LESS SOC RF TRANSMITTER

Brand: Silicon Laboratories | Category: Transmitter | Size: 0 MB

Table of Contents
3
1 System Overview

11
- Figure 1.1. Si4010 Block Diagram
  12
2 Test Circuit

13
- Figure 2.1. Test Block Diagram with 10-Pin MSOP
  13
3 Typical Application Schematic

14
4 Ordering Information

15
- Table 4.1. Product Selection Guide
  15
5 Top Markings

16
- Soic
  16
- Figure 1. Si4010 Top Marking
  16
- Table 1. Top Marking Explanation
  16
- Msop
  17
- Figure 2. Si4010 Top Marking
  17
- Table 2. Top Marking Explanation
  17
6 Pin Definitions

18
7 Package Specifications

22
- 10-Pin MSOP
  22
- Figure 7.1. 10-Pin MSOP Package
  22
- Table 7.1. Package Dimensions
  22
- 14-Pin SOIC Package
  23
- Figure 7.2. 14-Pin SOIC Package
  23
- Table 7.2. Package Dimensions
  23
8 PCB Land Pattern 10-Pin MSOP

24
- Figure 8.1. 10-Pin MSOP Recommended PCB Land Pattern
  24
- Table 8.1. 10-Pin MSOP Dimensions
  25
9 PCB Land Pattern 14-Pin SOIC Package

26
- Figure 9.1. 14-Pin SOIC Recommended PCB Land Pattern
  26
- Table 9.1. PCB Land Pattern Dimensions
  27
10 Electrical Characteristics

28
11 System Description

33
12 Power Amplifier

36
13 Output Data Serializer (ODS)

40
- Description
  40
- Timing
  40
- Figure 13.1. OOK Timing Example
  40
- Figure 13.2. FSK Timing Example
  40
- Register Description
  41
- SFR Definition 13.1. ODS_CTRL
  41
- SFR Definition 13.2. ODS_TIMING
  42
- SFR Definition 13.3. ODS_DATA
  43
- SFR Definition 13.4. ODS_RATEL
  43
- SFR Definition 13.5. ODS_RATEH
  44
- SFR Definition 13.6. ODS_WARM1
  44
- SFR Definition 13.7. ODS_WARM2
  45
14 LC Oscillator (LCOSC)

46
- Register Description
  46
- SFR Definition 14.1. LC_FSK
  46
15 Low Power Oscillator and System Clock Generator

47
- Register Description
  47
- SFR Definition 15.2. SYSGEN
  48
16 Crystal Oscillator (XO)

49
- Register Description
  49
17 Frequency Counter

50
18 Sleep Timer

54
19 Bandgap and LDO

54
20 Low Leakage HVRAM

54
21 Temperature Sensor

54
22 Microcontroller

55
- Figure 22.1. CIP-51 Block Diagram
  55
- SFR Definition 22.1. DPL
  61
- SFR Definition 22.2. DPH
  61
- SFR Definition 22.3. SP
  62
- SFR Definition 22.4. ACC
  62
- SFR Definition 22.5. B
  63
- SFR Definition 22.6. PSW
  64
23 Memory Organization

65
- Figure 23.1. Address Space Map after the Boot
  65
  - Program Memory
    66
  - Internal Data Memory
    66
  - External Data Memory
    66
  - General Purpose Registers
    66
  - Bit Addressable Locations
    67
  - Stack
    67
  - Special Function Registers (SFR)
    67
  - Registers Mapped to XDATA Address Space (XREG)
    67
  - NVM (OTP) Memory
    67
  - MTP (EEPROM) Memory
    68
24 System Boot and NVM Programming

69
25 On-Chip Registers

85
26 Interrupts

91
- MCU Interrupt Sources and Vectors
  92
- Interrupt Priorities
  92
- Interrupt Latency
  92
- Interrupt Register Descriptions
  93
- Table 26.1. Interrupt Summary
  93
- SFR Definition 26.1. IE
  94
- SFR Definition 26.2. IP
  95
- SFR Definition 26.3. EIE1
  96
- SFR Definition 26.4. EIP1
  97
- SFR Definition 26.5. INT_FLAGS
  98
  - External Interrupts
    99
- SFR Definition 26.6. PORT_INTCFG
  100
27 Power Management Modes

101
- Idle Mode
  101
- Stop Mode
  101
- SFR Definition 27.1. PCON
  102
28 AES Hardware Accelerator

103
- AES SFR Registers
  103
- SFR Definition 28.1. GFM_DATA
  104
- SFR Definition 28.2. GFM_CONST
  104
- SFR Definition 28.3. SBOX_DATA
  105
- SFR Definition 28.4. SYS_SET
  105
29 Reset Sources

106
- Device Boot Outline
  106
- External Reset
  106
- Software Reset
  107
30 Port Input/Output

108
- Figure 30.1. Device Package and Port Assignments
  108
  - Table 30.1. 10-Pin Mode
    109
  - Table 30.2. 14-Pin Mode
    109
  - Figure 30.2. GPIO[3:1] Functional Diagram
    110
  - Figure 30.3. Other GPIO Functional Diagram
    110
  - GPIO Pin Special Roles
    111
  - Table 30.3. GPIO Special Roles
    111
  - Matrix Mode Option
    112
  - Pullup Roff Option
    112
  - Figure 30.4. Push Button Organization in Matrix Mode
    113
  - Pullup Roff and Matrix Mode Option Control
    114
  - Special GPIO Modes Control
    115
  - Table 30.4. GPIO Special Roles Control and Order
    116
  - Figure 30.5. GPIO[5] LED Driver Block Diagram
    117
  - LED Driver on GPIO[5]
    117
- SFR Definition 30.1. P0
  118
- SFR Definition 30.2. P0CON
  119
- SFR Definition 30.3. P1
  119
- SFR Definition 30.4. P1CON
  120
- SFR Definition 30.5. P2
  120
- SFR Definition 30.6. PORT_CTRL
  121
- SFR Definition 30.7. PORT_SET
  122
31 Clock Output Generation

123
- Figure 31.1. Output Clock Generator Block Diagram
  123
  - Register Description
    124
- SFR Definition 31.1. CLKOUT_SET
  124
32 Control and System Setting Registers

126
- SFR Definition 32.1. GPR_CTRL
  126
- SFR Definition 32.2. GPR_DATA
  126
- SFR Definition 32.3. RBIT_DATA
  127
33 Real Time Clock Timer

128
- Figure 33.1. RTC Timer Block Diagram
  128
  - RTC Interrupt Flag Time Uniformity
    129
  - Register Description
    129
- SFR Definition 33.1. RTC_CTRL
  130
34 Timers 2 and 3

131
35 C2 Interface

148
36 IDE Development Environment and Debugging Chain

151
37 Additional Reference Resources

154
Document Change List

155
Contact Information

156

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Motherboard Microcontrollers Computer Hardware Control Unit Adapter

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Silicon Laboratories Si4010-GT Manuals

Silicon Laboratories Si4010-GT Manual (157 pages)

Table of Contents

1 System Overview

2 Test Circuit

3 Typical Application Schematic

4 Ordering Information

5 Top Markings

6 Pin Definitions

7 Package Specifications

8 PCB Land Pattern 10-Pin MSOP

9 PCB Land Pattern 14-Pin SOIC Package

10 Electrical Characteristics

11 System Description

12 Power Amplifier

13 Output Data Serializer (ODS)

14 LC Oscillator (LCOSC)

15 Low Power Oscillator and System Clock Generator

16 Crystal Oscillator (XO)

17 Frequency Counter

18 Sleep Timer

19 Bandgap and LDO

20 Low Leakage HVRAM

21 Temperature Sensor

22 Microcontroller

23 Memory Organization

24 System Boot and NVM Programming

25 On-Chip Registers

26 Interrupts

27 Power Management Modes

28 AES Hardware Accelerator

29 Reset Sources

30 Port Input/Output

31 Clock Output Generation

32 Control and System Setting Registers

33 Real Time Clock Timer

34 Timers 2 and 3

35 C2 Interface

36 IDE Development Environment and Debugging Chain

37 Additional Reference Resources

Document Change List

Contact Information

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