Clock Generation - Xilinx ZCU104 User Manual

Clock Generation

The ZCU104 board provides an IDT8T49N287 FemtoClock® NG octal universal frequency
translator (U182) clock generator.
Table 3-12: Clock Sources
Clock (Net) Name
HDMI_DRU_CLOCK
PS_REF_CLK
GTR_REF_CLK_USB3
GTR_REF_CLK_DP
CLK_300_P
GTR_REF_CLK_SATA
CLK_125
Table 3-13 lists the connectivity for each clock.
Table 3-13: Clock Connections, Source to XCZU7EV MPSoC
Clock Source Pin
U182.48
U182.47
U182.44
U182.27
U182.28
U182.23
U182.24
U182.40
U182.39
U182.37
U182.36
U182.34
U182.33
Notes:
1. U1 XCU7EV Bank 503 supports LVCMOS level inputs.
2. U1 MGT (I/O standards do not apply).
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Table 3-12
Frequency
156.25 MHz
33.33 MHz
26 MHz
27 MHz
300 MHz
125 MHz
125 MHz
Net Name
HDMI_DRU_CLOCK_P
HDMI_DRU_CLOCK_N
PS_REF_CLK
GTR_REF_CLK_USB3_P
GTR_REF_CLK_USB3_N
GTR_REF_CLK_DP_P
GTR_REF_CLK_DP_N
CLK_300_C_P
CLK_300_C_N
GTR_REF_CLK_SATA_P
GTR_REF_CLK_SATA_N
CLK_125_P
CLK_125_N
www.xilinx.com
Chapter 3: Board Component Descriptions
lists the frequency for each clock.
IDT8T49N287 U182
Clock Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
I/O Standard XCZU7EV (U1) Pin
(2)
(2)
(1)
LVCMOS18
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
LVDS
LVDS
U10
U9
R24
M27
M28
M31
M32
AH12
AJ12
P27
P28
H11
G11
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