Dpaux (Mio 27-30) - Xilinx ZCU104 User Manual

DPAUX (MIO 27-30)

[Figure 2-1, callout 27]
The Zynq UltraScale+ MPSoC provides a VESA DisplayPort 1.2 source-only controller that
supports up to two lanes of main link data at rates of 1.62 Gb/s, 2.70 Gb/s, or 5.40 Gb/s. The
DisplayPort standard defines an auxiliary channel that uses LVDS signaling at a 1 Mb/s data
rate, which is translated from single-ended MIO signals to the differential DisplayPort AUX
channel, DPAUX (see
Table 3-21: DPAUX/MIO Connections
XCZU7EV (U1) Pin
A33
A32
A31
A30
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Table 3-21). The DisplayPort circuit is shown in
Net Name
MIO30_DP_AUX_IN
MIO29_DP_OE
MIO28_DP_HPD
MIO27_DP_AUX_OUT
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Chapter 3: Board Component Descriptions
Figure
Level Shifter U114
Pin Name
2A1
1A2
2A2
1A1
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3-15.
Pin #
8
7
9
6
55