Xilinx ZCU104 User Manual page 20

The top-level block diagram is shown in
X-Ref Target - Figure 3-1
Processing System
RPU
GIC
Cortex-R5
32 KB I/D
128 KB TCM
Low Power Switch
256 KB
OCM
RGMII
4 x 1GE
ULPI
2 x USB 3.0
NAND x8
ONFI 3.1
2 x SD3.0/
eMMC4.51
Quad-SPI
x 8
2 x SPI
2 x CAN
2 x I2C
2 x UART
GPIOs
SYSMON
CSU
PMU
SHA3
AES-GCM
RSA
128 KB RAM
Battery
Low Power
Power
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
APU
Cortex-A53
32 KB I/D
Cortex-R5
32 KB I/D
128 KB TCM
ACP
LPD-DMA
Processor
BPU
System
DDRC (DDR4/3/3L, LPDDR3/4)
Full Power
Figure 3-1: Top-Level Block Diagram
www.xilinx.com
Chapter 3: Board Component Descriptions
Figure 3-1.
GIC
Cortex-A53 Cortex-A53 Cortex-A53
32 KB I/D 32 KB I/D 32 KB I/D
SCU
1 MB L2
SMMU/CCI
Central
Switch
FPD-DMA
32-bit/64-bit
M
64-bit
GPU
Mali-400 MP2
64 KB L2
PCIe Gen2
x1, x2, or x4
2 x SATA
v3.1
SGMII
USB 3.0
DisplayPort
v1.2 x1, x2
DisplayPort
Video and
Audio Interface
Programmable
Logic
100G
Interlaken
Ethernet
GFC
GTY GTH
Quad Quad
PCIe
To ACP
Gen4
S M S
128-bit
X16387-012618
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