Xilinx ZCU104 User Manual page 47

Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC (Cont'd)
XCZU7EV
(U1) Pin
K31
K32
K33
K34
L29
L30
L33
L34
Ethernet PHY Reset
The DP83867IRPAP PHY reset gate U169 is shown in
reset by the MAX16025 U22 MPSoC PS-side POR reset device (PS_POR_B) or the I2C0
connected U97 TCA6416A I/O expander pin 10 port P06 (GEM3_EXP_RESET_B).
X-Ref Target - Figure 3-10
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Net Name
MIO70_ENET_RX_CLK
MIO71_ENET_RX_D0
MIO72_ENET_RX_D1
MIO73_ENET_RX_D2
MIO74_ENET_RX_D3
MIO75_ENET_RX_CTRL
MIO76_ENET_MDC
MIO77_ENET_MDIO
Figure 3-10: Ethernet PHY Reset Circuit
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Chapter 3: Board Component Descriptions
DP83867 PHY U98
Pin #
43
44
45
46
47
53
20
21
Figure 3-10. The DP83867IRPAP can be
Send Feedback
Pin Name
RX_CLK
RX_DO
RX_D1
RX_D2
RX_D3
RX_DV_RX_CTRL
MDC
MDIO
X20255-013018
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