Xilinx ZCU104 User Manual page 72

FMC LPC
The FMC low pin count (LPC) connector J5 has its full LA[00:33] bus connected across the
XCZU7EV MPSoC PL banks 67 and 68.
The three FMC LPC clocks are connected as follows:
• FMC_LPC_GBTCLK0_M2C_C_P/N is connected to GTH bank 226 MGTREFCLK0
• FMC_LPC_CLK0_M2C_P/N is connected to PL bank 67 (LA[00:16]) GC pins E15/E14
• FMC_LPC_CLK1_M2C_P/N is connected to PL bank 68 (LA[17:33]) GC pins G10/F10
HDMI
Three PL-side GTH transceivers are dedicated for HDMI source and sink. Modes supported
are 4K, 2K at 60 f/s, and 2160p60. External circuitry for interfacing TMDS signals with the
GTH transceivers is required.
connections, respectively.
Table 3-26: GTH Bank 226 Interface Connections
XCZU7EV XCZU7EV Pin
(U1) Pin Name
U6 MGTHTXP0
U5 MGTHTXN0
V4 MGTHRXP0
V3 MGTHRXN0
T4 MGTHTXP1
T3 MGTHTXN1
U2 MGTHRXP1
U1 MGTHRXN1
R6 MGTHTXP2
R5 MGTHTXN2
R2 MGTHRXP2
R1 MGTHRXN2
N6 MGTHTXP3
N5 MGTHTXN3
P4 MGTHRXP3
P3 MGTHRXN3
V8 MGTREFCLK0P
V7 MGTREFCLK0N
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Table 3-26 and
Schematic Net Name
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not Connected
Not Connected
Not Connected
Not Connected
FMC_LPC_GBTCLK0_M2C_C_P
FMC_LPC_GBTCLK0_M2C_C_N
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Chapter 3: Board Component Descriptions
Table 3-27 list MGTH banks 226 and 227
Connected To
(2)
Pin No. Pin Name
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
(1)
D4 GBTCLK0_M2C_P
(1)
D5 GBTCLK0_M2C_N
Device
NA
NA
FMC LPC J5
72
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