Xilinx ZCU104 User Manual page 77

Table 3-29: J5 LPC FMC Section C and D Connections to XCZU7EV U1
J5
Schematic Net Name
Pin
C2 FMC_LPC_DP0_C2M_P
C3 FMC_LPC_DP0_C2M_N
C6 FMC_LPC_DP0_M2C_P
C7 FMC_LPC_DP0_M2C_N
C10 FMC_LPC_LA06_P
C11 FMC_LPC_LA06_N
C14 FMC_LPC_LA10_P
C15 FMC_LPC_LA10_N
C18 FMC_LPC_LA14_P
C19 FMC_LPC_LA14_N
C22 FMC_LPC_LA18_CC_P
C23 FMC_LPC_LA18_CC_N
C26 FMC_LPC_LA27_P
C27 FMC_LPC_LA27_N
C30 FMC_LPC_IIC_SCL
C31 FMC_LPC_IIC_SDA
C34 GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
U1
I/O J5
FPGA
Standard Pin
Pin
(2)
H4 D1
(2)
H3 D4
(2)
G2 D5
(2)
G1 D8
LVDS H19 D9
LVDS G19 D11
LVDS L15 D12
LVDS K15 D14
LVDS C13 D15
LVDS C12 D17
LVDS D11 D18
LVDS D10 D20
LVDS A8 D21
LVDS A7 D23
D24
D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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Chapter 3: Board Component Descriptions
Schematic Net Name
VADJ_FMC_PGOOD
FMC_LPC_GBTCLK0_M2C_P
FMC_LPC_GBTCLK0_M2C_N
FMC_LPC_LA01_CC_P
FMC_LPC_LA01_CC_N
FMC_LPC_LA05_P
FMC_LPC_LA05_N
FMC_LPC_LA09_P
FMC_LPC_LA09_N
FMC_LPC_LA13_P
FMC_LPC_LA13_N
FMC_LPC_LA17_CC_P
FMC_LPC_LA17_CC_N
FMC_LPC_LA23_P
FMC_LPC_LA23_N
FMC_LPC_LA26_P
FMC_LPC_LA26_N
F4232_TCK
FPGA_TDO_FMC_TDI_LS
FMC_TDO
UTIL_3V3
FT4232_TMS
NC
GA1=0=GND
UTIL_3V3
UTIL_3V3
UTIL_3V3
U1
I/O
FPGA
Standard
Pin
(1)
LVDS V8
(1)
LVDS V7
LVDS H18
LVDS H17
LVDS K17
LVDS J17
LVDS H16
LVDS G16
LVDS G15
LVDS F15
LVDS F11
LVDS E10
LVDS B11
LVDS A11
LVDS B9
LVDS B8
77
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