Xilinx ZCU104 User Manual page 32

Table 3-4: DDR4 SODIMM Socket J1 Connections to FPGA PL Banks 64, 65, and 66 (Cont'd)
XCZU7EV
(U1) Pin
AH18 DDR4_SODIMM_DM0_B
AD15 DDR4_SODIMM_DM1_B
AM16 DDR4_SODIMM_DM2_B
AP18 DDR4_SODIMM_DM3_B
AE18 DDR4_SODIMM_DM4_B
AH22 DDR4_SODIMM_DM5_B
AL20 DDR4_SODIMM_DM6_B
AP19 DDR4_SODIMM_DM7_B
AH14 DDR4_SODIMM_DQS0_T
AJ14 DDR4_SODIMM_DQS0_C
AA16 DDR4_SODIMM_DQS1_T
AA15 DDR4_SODIMM_DQS1_C
AK15 DDR4_SODIMM_DQS2_T
AK14 DDR4_SODIMM_DQS2_C
AM14 DDR4_SODIMM_DQS3_T
AN14 DDR4_SODIMM_DQS3_C
AA18 DDR4_SODIMM_DQS4_T
AB18 DDR4_SODIMM_DQS4_C
AF23 DDR4_SODIMM_DQS5_T
AG23 DDR4_SODIMM_DQS5_C
AK22 DDR4_SODIMM_DQS6_T
AK23 DDR4_SODIMM_DQS6_C
AM21 DDR4_SODIMM_DQS7_T
AN21 DDR4_SODIMM_DQS7_C
AH11 DDR4_SODIMM_CK0_T
AJ11 DDR4_SODIMM_CK0_C
AJ9 DDR4_SODIMM_CK1_T
AK9 DDR4_SODIMM_CK1_C
AB13 DDR4_SODIMM_CKE0
AL13 DDR4_SODIMM_CKE1
AF10 DDR4_SODIMM_ODT0
AK13 DDR4_SODIMM_ODT1
AF11 DDR4_SODIMM_RAS_B
AE12 DDR4_SODIMM_CAS_B
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Net Name I/O Standard
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
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Chapter 3: Board Component Descriptions
DDR4 SODIMM Memory J1
Pin Number
12
33
54
75
178
199
220
241
13
11
34
32
55
53
76
74
179
177
200
198
221
219
242
240
139
137
140
138
109
110
155
161
152
156
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Pin Name
DM0_N/DBI0_N
DM1_N/DBI1_N
DM2_N/DBI2_N
DM3_N/DBI3_N
DM4_N/DBI4_N
DM5_N/DBI5_N
DM6_N/DBI6_N
DM7_N/DBI7_N
DQS0_T
DQS0_C
DQS1_T
DQS1_C
DQS2_T
DQS2_C
DQS3_T
DQS3_C
DQS4_T
DQS4_C
DQS5_T
DQS5_C
DQS6_T
DQS6_C
DQS7_T
DQS7_C
CK0_C
CK0_T
CK1_C/NF
CK1_T/NF
CKE0
CKE1
ODT0
ODT1
RAS_N/A16
CAS_N/A15
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