Xilinx ZCU104 User Manual page 75

Bank 505 DP (DisplayPort) lanes 0 and 1 TX support the 2-channel source only PS-side
DisplayPort circuitry described in
Bank 505 USB0 lane 2 supports the USB3.0 interface described in
USB 2.0 ULPI PHY, page
Bank 505 SATA1 lane 3 supports the M.2 SATA connector U170 as shown in
Bank 505 reference clocks are connected to the U182 8T49N287 clock generator as
described in Clock Generation, page
Bank 505 connections are shown in
Table 3-28: PS-GTR Bank 505 Interface Connections
XCZU7EV
(U1) Pin XCZU7EV Pin Name
U29 PS_MGTRTXP0
U30 PS_MGTRTXN0
R29 PS_MGTRTXP1
R30 PS_MGTRTXN1
U33 PS_MGTRRXP0
U34 PS_MGTRRXN0
T31 PS_MGTRRXP1
T32 PS_MGTRRXN1
P31 PS_MGTRTXP2
P32 PS_MGTRTXN2
R33 PS_MGTRRXP2
R34 PS_MGTRRXN2
N29 PS_MGTRTXP3
N30 PS_MGTRTXN3
N33 PS_MGTRRXP3
N34 PS_MGTRRXN3
T27 PS_MGTREFCLK0P
T28 PS_MGTREFCLK0N
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
DPAUX (MIO 27-30), page
35.
44.
Table 3-28.
(2)
Schematic Net Name
(1)
GT0_DP_TX_P
(1)
GT0_DP_TX_N
(1)
GT1_DP_TX_P
(1)
GT1_DP_TX_N
NC
NC
NC
NC
(1)
GT2_USB0_TX_P
(1)
GT2_USB0_TX_N
GT2_USB0_RX_P
GT2_USB0_RX_N
(1)
GT3_SATA1_TX_P
(1)
GT3_SATA1_TX_N
(1)
GT3_SATA1_RX_P
(1)
GT3_SATA1_RX_N
NC
NC
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Chapter 3: Board Component Descriptions
55.
USB 3.0 Transceiver and
Connected To
Pin No. Pin Name
4 ML_LANE1_P
6 ML_LANE1_N
1 ML_LANE0_P
3 ML_LANE0_N
NA NA
NA NA
NA NA
NA NA
9 SSTXP
8 SSTXN
6 SSRXP
5 SSRXN
2 SATA_A_P
3 SATA_A_N
6 SATA_B_P
5 SATA_B_N
NA NA
NA NA
Figure 3-7.
Device
DisplayPort
connector P11
NA
USB J96
M.2 U170
NA
75
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