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7.3
Standard Event Register
Standard Event Register
Bit Masking
IM 760301-17E
7
6
5
4
3
2
PON
URQ
CME EXE DDE QYERQCOPC
Bit 7 PON (Power ON)
Set to 1 when the power is turned ON.
Bit 6 URQ (User Request)
Not used (always 0)
Bit 5 CME (Command Error)
Set to 1 when the command syntax is incorrect.
Example
Received a command name with a spelling error or character data not in
the selection.
Bit 4 EXE (Execution Error)
Set to 1 when the command syntax is correct but the command cannot be executed in
the current state.
Example
Received a command with a parameter outside the range or a command
dealing with an unsupported option.
Bit 3 DDE (Device Error)
Set to 1 when execution of the command is not possible due to an internal problem in the
instrument that is not a command error or an execution error.
Bit 2 QYE (Query Error)
Set to 1 if the output queue is empty or if the data is missing even after a query has been
sent.
Example
No response data; data is lost due to an overflow in the output queue.
Bit 1 RQC (Request Control)
Not used (always 0)
Bit 0 OPC (Operation Complete)
Set to 1 when the operation designated by the *OPC command (see chapter 6) has been
completed.
If you wish to mask a certain bit of the standard event register so that it does not cause
bit 5 (ESB) of the status byte to change, set the corresponding bit of the standard event
enable register to 0. For example, to mask bit 2 (QYE) so that ESB is not set to 1, even
if a query error occurs, set bit 2 of the standard event enable register to 0. This can be
done using the *ESE command. To query whether each bit of the standard event enable
register is 1 or 0, use the *ESE?. For details on the *ESE command, see chapter 6.
1
0
1
2
3
4
5
6
7
App
Index
7-5
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