Vga Signal Timing - Xilinx Spartan-3A User Manual

Chapter 6: VGA Display Port
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The Spartan-3A/3AN Starter Kit board uses 12 bits per pixel,
producing one of the 4,096 possible colors. The controller indexes into the video data buffer
as the beams move across the display. The controller then retrieves and applies video data
to the display at precisely the time the electron beam is moving across a given pixel.
As shown in
sync (VS) timing signals and coordinates the delivery of video data on each pixel clock. The
pixel clock defines the time available to display one pixel of information. The VS signal
defines the refresh frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display's phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal retrace frequency.

VGA Signal Timing

The signal timings in
25 MHz pixel clock and 60 Hz ± 1 refresh.
the timing symbols. The timing for the sync pulse width (T
intervals (T
back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 6-2: 640x480 Mode VGA Timing
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
60
Figure 6-2, the VGA controller generates the horizontal sync (HS) and vertical
Table 6-2
and T ) is based on observations from various VGA displays. The front and
FP BP
Symbol Parameter
T
Sync pulse time
S
T
Display time
DISP
T Pulse width
PW
T Front porch
FP
T Back porch
BP
T
pw
www.xilinx.com
are derived for a 640-pixel by 480-row display using a
Figure 6-3
Vertical Sync
Time Clocks
16.7 ms 416,800
15.36 ms 384,000
64 µs 1,600
320 µs 8,000
928 µs 23,200
T
S
T
disp
Figure 6-3: VGA Control Timing
Spartan-3A/3AN Starter Kit Board User Guide
shows the relation between each of
) and front and back porch
PW
Horizontal Sync
Lines Time
521 32 µs
480 25.6 µs
2 3.84 µs
10 640 ns
29 1.92 µs
T
fp
UG230_c6_03_021706
UG334 (v1.0) May 28, 2007
R
Clocks
800
640
96
16
48
T
bp