Vga Signal Timing - Xilinx Spartan-3 User Manual

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Modern VGA displays support multiple display resolutions, and the VGA controller
dictates the resolution by producing timing signals to control the raster patterns. The
controller produces TTL-level synchronizing pulses that set the frequency at which current
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The Spartan-3 Starter Kit board uses three bits per pixel, producing
one of the eight possible colors shown in
data buffer as the beams move across the display. The controller then retrieves and applies
video data to the display at precisely the time the electron beam is moving across a given
pixel.
As shown in
(vertical sync) timings signals and coordinates the delivery of video data on each pixel
clock. The pixel clock defines the time available to display one pixel of information. The VS
signal defines the "refresh" frequency of the display, or the frequency at which all
information on the display is redrawn. The minimum refresh frequency is a function of the
display's phosphor and electron beam intensity, with practical refresh frequencies in the
60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh
frequency defines the horizontal "retrace" frequency.

VGA Signal Timing

The signal timings in
25 MHz pixel clock and 60 Hz ±1 refresh.
timing symbols. The timing for the sync pulse width (T
intervals (T
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 5-3: 640x480 Mode VGA Timing
24
Figure 5-2, the VGA controller generates the HS (horizontal sync) and VS
Table 5-3
and T ) are based on observations from various VGA displays. The front
FP BP
Symbol Parameter
T Sync pulse time
S
T Display time
DISP
T Pulse width
PW
T Front porch
FP
T Back porch
BP
T
PW
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Table 5-2. The controller indexes into the video
are derived for a 640-pixel by 480-row display using a
Figure 5-3 shows the relation between each of the
Vertical Sync
Time Clocks
16.7 ms 416,800
15.36 ms 384,000
64 µs
1,600
320 µs
8,000
928 µs
23,200
T
S
T
DISP
Figure 5-3: VGA Control Timing
Spartan-3 Starter Kit Board User Guide
Chapter 5: VGA Port
) and front and back porch
PW
Horizontal Sync
Lines Time
32 µs
521
25.6 µs
480
3.84 µs
2
10 640 ns
1.92 µs
29
T
FP
UG130_c5_03_051305
UG130 (v1.1) May 13, 2005
Clocks
800
640
96
16
48
T
BP