Instruction Cache - Motorola MC68030 User Manual

On-Chip Cache Memories
An external access is defined as "cachable" for either the instruction or data cache when all
the following conditions apply:
• The cache is enabled with the appropriate bit in the CACR set.
• The CDIS signal is negated.
• The CIIN signal is negated for the access.
• The CIOUT signal is negated for the access.
• The MMU validates the access.
Because both the data and instruction caches are referenced by logical addresses, they
should be flushed during a task switch or at any time the logical-to-physical address
mapping changes, including when the MMU is first enabled. In addition, if a page descriptor
is currently marked as valid and is later changed to the invalid type (due to a context switch
or a page replacement operation) entries in the on-chip instruction or data cache
corresponding to the physical page must be first cleared (invalidated) . Otherwise, if on-chip
cache entries are valid for pages with descriptors in memory marked invalid, processor
operation is unpredictable.
Data read and write accesses to the same address should also have consistent cachability
status to ensure that the data in the cache remains consistent with external memory. For
example, if CIOUT is negated for read accesses within a page and the MMU configuration
is changed so that CIOUT is subsequently asserted for write accesses within the same
page, those write accesses do not update data in the cache, and stale data may result.
Similarly, when the MMU maps multiple logical addresses to the same physical address, all
accesses to those logical addresses should have the same cachability status.

6.1.1 Instruction Cache

The instruction cache is organized with a line size of four long words, as shown in Figure 6-
2. Each of these long words is considered a separate cache entry as each has a separate
valid bit. All four entries in a line have the same tag address. Burst filling all four long words
can be advantageous when the time spent in filling the line is not long relative to the
equivalent bus-cycle time for four nonburst long-word accesses, because of the probability
that the contents of memory adjacent to or close to a referenced operand or instruction is
also required by subsequent accesses. Dynamic RAMs supporting fast access modes
(page, nibble, or static column) are easily employed to support the MC68030 burst mode.
6-4 MC68030 USER'S MANUAL MOTOROLA