Motorola MC68030 User Manual page 225

S0
CLK
A31-A0
FC2-FC0
SIZ1-SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D0
BERR
HALT
Figure 7-48. Breakpoint Acknowledge Cycle Timing (Exception Signaled)
Another signal that is used for bus exception control is HALT. This signal can be asserted
by an external device for debugging purposes to cause single bus cycle operation or (in
combination with BERR) a retry of a bus cycle in error.
MOTOROLA
S2 Sw Sw
READ WITH BUS ERROR ASSERTED
MC68030 USER'S MANUAL
Sw S4
INTERNAL
PROCESSING
Bus Operation
S2
S0 S4
STACK WRITE
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