Bus Operation
CONTROLLER
ADDRESS DEVICE
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) DRIVE R/W TO READ
3) DRIVE ADDRESS ON A31–A0
4) DRIVE FUNCTION ON FC2–FC0
5) DRIVE SIZE (SIZ1–SIZ0) (FOUR BYTES)
6) CACHE INHIBIT OUT (CIOUT) BECOMES
VALID
7) ASSERT ADDRESS STROBE (AS)
8) ASSERT CACHE BURST REQUEST (CBREQ)
9) ASSERT DATA STROBE (DS)
10) ASSERT DATA BUFFER ENABLE (DBEN)
ACQUIRE DATA
1) SAMPLE CACHE INHIBIT IN (CIIN)
AND CACHE BURST ACKNOWLEDGE
(CBACK)
2) LATCH DATA
END OF BURST
1) NEGATE AS AND DS
2) NEGATE DBEN
START NEXT CYCLE
Figure 7-37. Burst Operation Flowchart — Four Long Words Transferred
not to be cached, CIIN must be asserted at the same time as STERM. The assertion of
CIIN also has the effect of aborting the burst operation.
7-64
1) DECODE ADDRESS
2) PLACE DATA ON D31-D0
3) ASSERT SYNCHRONOUS TERMINATION (STERM)
4) ASSERT CACHE BURST ACKNOWLEDGE (CBACK)
1) REMOVE DATA FROM D31-D0
2) NEGATE STERM (IF NECESSARY)
3) NEGATE CBACK (IF NECESSARY)
WHEN 4 LONG WORDS TRANSFERRED
MC68030 USER'S MANUAL
EXTERNAL DEVICE
PRESENT DATA
TERMINATE CYCLE
UNTIL 4 LONG WORDS TRANSFERRED
MOTOROLA