Motorola MC68030 User Manual page 240

Bus Operation
S0
CLK
A31-A0
FC2-FC0
SIZ1–SIZ0
R/W
ECS
OCS
AS
DS
STERM
CIIN
CIOUT
CBREQ
CBACK
D31–D0
BERR
HALT
The single-cycle mode allows the user to proceed through (and debug) external processor
operations, one bus cycle at a time. Figure 7-57 shows the timing requirements for a single-
cycle operation. Since the occurrence of a bus error while HALT is asserted causes a retry
operation, the user must anticipate retry cycles while debugging in the single-cycle mode.
The single-step operation and the software trace capability allow the system debugger to
trace single bus cycles, single instructions, or changes in program flow. These processor
capabilities, along with a software debugging package, give complete debugging flexibility.
7-94
S1 S2 S3
READ
Figure 7-56. Late Retry Operation for a Burst
MC68030 USER'S MANUAL
S0
HALT
S1 S2 S3 S4
RETRY
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