Motorola MC68030 User Manual page 141

On-Chip Cache Memories
the read cycle in error is made only to fill the data cache (the data is not part of the target
operand), no exception occurs, but the corresponding entry is marked invalid. For the
instruction cache, the processor marks the entry as invalid, but only takes an exception if
the execution unit attempts to use the instruction word(s).
6.1.3.2 BURST MODE FILLING. Burst mode filling is enabled by bits in the cache control
register. The data burst enable bit must be set to enable burst filling of the data cache.
Similarly, the instruction burst enable bit must be set to enable burst filling of the instruction
cache. When burst filling is enabled and the corresponding cache is enabled, the bus
controller requests a burst mode fill operation in either of these cases:
• A read cycle for either the instruction or data cache misses due to the indexed tag not
matching.
• A read cycle tag matches, but all long words in the line are invalid.
The bus controller requests a burst mode fill operation by asserting the cache burst request
signal (CBREQ). The responding device may sequentially supply one to four long words of
cachable data, or it may assert the cache inhibit input signal (CIIN) when the data in a long
word is not cachable. If the responding device does not support the burst mode and it
terminates cycles with STERM, it should not acknowledge the request with the assertion of
the cache burst acknowledge (CBACK) signal. The MC68030 ignores the assertion of
CBACK during cycles terminated with DSACKx.
The cache burst request signal (CBREQ) requests burst mode operation from the
referenced external device. To operate in the burst mode, the device or external hardware
must be able to increment the low-order address bits if required, and the current cycle must
be a 32-bit synchronous transfer (STERM must be asserted) as described in Section 7 Bus
Operation . The device must also assert CBACK (at the same time as STERM) at the end
of the cycle in which the MC68030 asserts CBREQ. CBACK causes the processor to
continue driving the address and bus control signals and to latch a new data value for the
next cache entry at the completion of each subsequent cycle (as defined by STERM), for a
total of up to four cycles (until four long words have been read).
When a cache burst is initiated, the first cycle attempts to load the cache entry
corresponding to the instruction word or data item explicitly requested by the execution unit.
The subsequent cycles are for the subsequent entries in the cache line. In the case of a
misaligned transfer when the operand spans two cache entries within a cache line, the first
cycle corresponds to the cache entry containing the portion of the operand at the lower
address.
Figure 6-11 illustrates the four cycles of a burst operation and shows that the second, third,
and fourth cycles are run in burst mode. A distinction is made between the first cycle of a
burst operation and the subsequent cycles because the first cycle is requested by the
microsequencer and the burst fill cycles are requested by the bus controller. Therefore,
when data from the first cycle is returned, it is immediately available for the execution unit
(EU). However, data from the burst fill cycles is not available to the EU until the burst
operation is complete. Since the microsequencer makes two separate requests for
misaligned data operands, only the first portion of the misaligned operand returned during a
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