Double Bus Fault - Motorola MC68030 User Manual

Bus Operation
When the processor completes a bus cycle with the HALT signal asserted, the data bus is
placed in the high-impedance state, and bus control signals are driven inactive (not high-
impedance state); the address, function code, size, and read/write signals remain in the
same state. The halt operation has no effect on bus arbitration (refer to 7.7 Bus
Arbitration). When bus arbitration occurs while the MC68030 is halted, the address and
control signals are also placed in the high-impedance state. Once bus mastership is
returned to the MC68030, if HALT is still asserted, the address, function code, size, and
read/write signals are again driven to their previous states. The processor does not service
interrupt requests while it is halted, but it may assert the IPEND signal as appropriate.

7.5.4 Double Bus Fault

When a bus error or an address error occurs during the exception processing sequence for
a previous bus error, a previous address error, or a reset exception, the bus or address error
causes a double bus fault. For example, the processor attempts to stack several words
containing information about the state of the machine while processing a bus error
exception. If a bus error exception occurs during the stacking operation, the second error is
considered a double bus fault. Only an external reset operation can restart a halted
processor. However, bus arbitration can still occur (refer to 7.7 Bus Arbitration).
The MC68030 indicates that a double bus fault condition has occurred by continuously
asserting the STATUS signal until the processor is reset. The processor asserts STATUS
for one, two, or three clock periods to signal other microsequencer status indications. Refer
to Section 12 Applications Information for a description of the interpretation of the
STATUS signal.
A second bus error or address error that occurs after exception processing has completed
(during the execution of the exception handler routine or later) does not cause a double bus
fault. A bus cycle that is retried does not constitute a bus error or contribute to a double bus
fault. The processor continues to retry the same bus cycle as long as the external hardware
requests it.
7-96 MC68030 USER'S MANUAL MOTOROLA