Changing Privilege Level - Motorola MC68030 User Manual

Processing States
The bus cycles for an instruction executed at the user privilege level are classified as user
references, and the values of the function codes on FC0-FC2 specify user address spaces.
The memory management unit of the processor, when it is enabled, uses the value of the
function codes to distinguish between user and supervisor activity and to control access to
protected portions of the address space. While the processor is at the user level, references
to the system stack pointer implicitly, or to address register seven (A7) explicitly, refer to the
user stack pointer (USP).

4.1.3 Changing Privilege Level

To change from the user to the supervisor privilege level, one of the conditions that causes
the processor to perform exception processing must occur. This causes a change from the
user level to the supervisor level and can cause a change from the master mode to the
interrupt mode. Exception processing saves the current values of the S and M bits of the
status register (along with the rest of the status register) on the active supervisor stack, and
then sets the S bit, forcing the processor into the supervisor privilege level. When the
exception being processed is an interrupt and the M bit is set, the M bit is cleared, putting
the processor into the interrupt mode. Execution of instructions continues at the supervisor
level to process the exception condition.
To return to the user privilege level, a system routine must execute one of the following
instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. The MOVE, ANDI,
EORI, and ORI to SR and RTE instructions execute at the supervisor privilege level and can
modify the S bit of the status register. After these instructions execute, the instruction
pipeline is flushed and is refilled from the appropriate address space. This is indicated
externally by the assertion of the REFILL signal.
The RTE instruction returns to the program that was executing when the exception occurred.
It restores the exception stack frame saved on the supervisor stack. If the frame on top of
the stack was generated by an interrupt, trap, or instruction exception, the RTE instruction
restores the status register and program counter to the values saved on the supervisor
stack. The processor then continues execution at the restored program counter address and
at the privilege level determined by the S bit of the restored status register. If the frame on
top of the stack was generated by a bus fault (bus error or address error exception), the RTE
instruction restores the entire saved processor state from the stack.
4-4 MC68030 USER'S MANUAL MOTOROLA