Motorola MC68030 User Manual page 193

State 2
During state 2 (S2), the processor drives DBEN active to enable external data buffers. The
selected device uses R/W, SIZ0–SIZ1, A0–A1, and DS to place information on the data
bus. Any or all of the bytes (D24–D31, D16–D23, D8–D15, and D0–D7) are selected by
SIZ0–SIZ1 and A0–A1. Concurrently, the selected device may assert the DSACKx
signals.
State 3
As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting
the asynchronous input setup time requirement), data is latched on the next falling edge
of the clock, and the cycle terminates. If DSACKx is not recognized by the start of S3, the
processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait
states are inserted, both DSACK0 and DSACK1 must remain negated throughout the
asynchronous input setup and hold times around the end of S2. If wait states are added,
the processor continues to sample the DSACKx signals on the falling edges of the clock
until one is recognized.
State 4
The processor samples the level of CIIN at the beginning of S4. At the end of S4, the
processor latches the incoming data.
State 5
The processor negates AS, DS, and DBEN during S5. If more than one read cycle is
required to read in the operand(s), S0–S5 are repeated for each read cycle. When
finished reading, the processor holds the address, R/W, and FC0–FC2 valid in
preparation for the write portion of the cycle.
The external device keeps its data and DSACKx signals asserted until it detects the
negation of AS or DS (whichever it detects first). The device must remove the data and
negate DSACKx within approximately one clock period after sensing the negation of AS
or DS. DSACKx signals that remain asserted beyond this limit may be prematurely
detected for the next portion of the operation.
Idle States
The processor does not assert any new control signals during the idle states, but it may
internally begin the modify portion of the cycle at this time. S6-S11 are omitted if no write
cycle is required. If a write cycle is required, the R/W signal remains in the read mode until
S6 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not
driven until S8.
MOTOROLA MC68030 USER'S MANUAL
Bus Operation
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