Motorola MC68030 User Manual page 30

The program counter (PC) contains the address of the next instruction to be executed by the
MC68030. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate.
31
31
31
31
31
31
31
31
Figure 1-3. Supervisor Programming Model Supplement
The status register, SR, (see Figure 1-4) stores the processor status. It contains the
condition codes that reflect the results of a previous operation and can be used for
conditional instruction execution in a program. The condition codes are extend (X), negative
(N), zero (Z), overflow (V), and carry (C). The user byte containing the condition codes is the
only portion of the status register information available in the user privilege level, and it is
referenced as the CCR in user programs. In the supervisor privilege level, software can
access the full status register, including the interrupt priority mask (three bits) as well as
additional control bits. These bits indicate whether the processor is in:
1. One of two trace modes (T1, T0)
2. Supervisor or user privilege level (S)
3. Master or interrupt mode (M)
The vector base register (VBR) contains the base address of the exception vector table in
memory. The displacement of an exception vector is added to the value in this register to
access the vector table.
MOTOROLA
16 15
16 15
15
8 7
15
MC68030 USER'S MANUAL
0
INTERRUPT
A7' (ISP)
STACK POINTER
0
MASTER STACK
A7" (MSP)
POINTER
0
(CCR) SR STATUS REGISTER
0
VECTOR BASE
VBR
REGISTER
0
SFC
ALTERNATE FUNCTION
CODE REGISTERS
DFC
0
CACHE CONTROL
CACR
REGISTER
0
CACHE ADDRESS
CAAR
REGISTER
0
ACCESS
CONTROL
AC0
REGISTER 0
0
ACCESS
CONTROL
AC1
REGISTER 1
0
ACU STATUS
ACUSR
REGISTER
Introduction
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