Motorola MC68030 User Manual page 206

Bus Operation
State 3
The processor negates AS, DS, and DBEN during S3. If more than one read cycle is
required to read in the operand(s), S0–S3 are repeated accordingly. When finished with
the read cycle, the processor holds the address, R/W, and FC0–FC2 valid in preparation
for the write portion of the cycle.
The external device must keep its data asserted throughout the synchronous hold time for
data from the beginning of S3. The device must remove the data within one-clock cycle
after asserting STERM to avoid bus contention. It must also negate STERM within two
clocks after asserting STERM; otherwise, the processor may inadvertently use STERM
for the next bus cycle.
Idle States
The processor does not assert any new control signals during the idle states, but it may
begin the modify portion of the cycle at this time. The R/W signal remains in the read mode
until S4 to prevent bus conflicts with the preceding read portion of the cycle; the data bus
is not driven until S6.
State 4
The processor asserts ECS and OCS in S4 to indicate that an external cycle is beginning.
The processor drives R/W low for a write cycle. CIOUT also becomes valid, indicating the
state of the MMU CI bit in the address translation descriptor or in the appropriate TTx
register. Depending on the write operation to be performed, the address lines may change
during S4.
State 5
In state 5 (S5), the processor asserts AS to indicate that the address on the address bus
is valid. The processor also asserts DBEN during S5, which can be used to enable
external data buffers.
State 6
During S6, the processor places the data to be written onto the D0–D31.
The selected device uses R/W, CLK, SIZ0–SIZ1, and A0–A1 to latch data from the
appropriate byte(s) of the data bus (D24–D31, D16–D23, D8–D15, and D0–D7). SIZ0–
SIZ1 and A0–A1 select the data bus sections. The device asserts STERM when it has
successfully stored the data. If the device does not assert STERM by the rising edge of
S6, the processor inserts wait states until it is recognized. The processor asserts DS at
the end of S6 if wait states are inserted. Note that for zero-wait-state synchronous write
cycles, DS is not asserted.
7-60 MC68030 USER'S MANUAL MOTOROLA