Motorola MC68030 User Manual page 156

REGISTER
MULTIPLEXER
EXTERNAL
DATA BUS
ADDRESS
xxxxxxxx0
INCREASING
MEMORY
ADDRESSES
xxxxxxxx0
2
a
xxxxxxxx0
1
2
3
Figure 7-4. MC68030 Interface to Various Port Sizes
Table 7-4 lists the bytes required on the data bus for read cycles that are cachable. The
entries shown as OPn are portions of the requested operand that are read or written during
that bus cycle and are defined by SIZ0, SIZ1, A0, and A1 for the bus cycle. The PRn and
the Nn bytes correspond to the previous and next bytes in memory, respectively, that must
be valid on the data bus for the specified port size (long word or word) so that the internal
caches operate correctly. (For cachable accesses, the MC68030 assumes that all portions
of the data bus for a given port size are valid.) This same table applies to noncachable read
cycles except that the bytes labeled PRn and Nn are not required and can be replaced by
"don't cares".
Table 7-2. Size Signal
Encoding
SIZ1
0
1
1
0
MOTOROLA
OP0 OP1
0 1
ROUTING AND DUPLICATION
D31- D24 D23-D16
BYTE 0 BYTE 1
BYTE 0 BYTE 1
BYTE 2 BYTE 3
b
BYTE 0
BYTE 1
8-BIT PORT
BYTE 2
BYTE 3
SIZ0 Size
1 Byte
0 Word
1 3 Bytes
0 Long Word
MC68030 USER'S MANUAL
OP2 OP3
2 3
D15-D8 D7-D0
BYTE 2 BYTE 3
16-BIT PORT
Table 7-3. Address Offset
Encodings
A1
0
0
1
1
Bus Operation
INTERNAL TO
THE MC68EC030
EXTERNAL BUS
32-BIT PORT
FIG 7-4
A0 Offset
0 +0 Bytes
1 +1 Byte
0 +2 Bytes
1 +3 Bytes
7-9