Motorola MC68030 User Manual page 143

On-Chip Cache Memories
The processor does not assert CBREQ if any of the following conditions exist:
• The appropriate cache is not enabled
• Burst filling for the cache is not enabled
• The cache freeze bit for the appropriate cache is set
• The current operation is the read portion of a read-modify-write operation
• The MMU has inhibited caching for the current page
• The cycle is for the first access of an operand that spans two cache lines (crosses a
modulo 16 boundary)
Additionally, the assertion of CIIN and BERR and the premature negation of CBACK affect
burst operation as described in the following paragraphs.
The assertion of CIIN during the first cycle of a burst operation causes the data to be latched
by the processor, and if the requested operand is aligned (the entire operand is latched in
the first cycle), the data is passed on to the instruction pipe or execution unit. However, the
data is not loaded into its corresponding cache. In addition, the MC68030 negates CBREQ,
and the burst operation is aborted. If a portion of the requested operand remains to be read
(due to misalignment), a second read cycle is initiated at the appropriate address with
CBREQ negated.
The assertion of CIIN during the second, third, or fourth cycle of a burst operation prevents
the data during that cycle from being loaded into the appropriate cache and causes CBREQ
to negate, aborting the burst operation. However, if the data for the cycle contains part of
the requested operand, the execution unit uses that data.
The premature negation of the CBACK signal during the burst operation causes the current
cycle to complete normally, loading the data successfully transferred into the appropriate
cache. However, the burst operation aborts and CBREQ negates.
A bus error occurring during a burst operation also causes the burst operation to abort. If the
bus error occurs during the first cycle of a burst (i.e., before burst mode is entered), the data
read from the bus is ignored, and the entire associated cache line is marked "invalid". If the
access is a data cycle, exception processing proceeds immediately. If the cycle is for an
instruction fetch, a bus error exception is made pending. This bus error is processed only if
the execution unit attempts to use either instruction word. Refer to 11.2.2 Instruction Pipe
for more information about pipeline operation.
For either cache, when a bus error occurs after the burst mode has been entered (that is,
on the second cycle or later), the cache entry corresponding to that cycle is marked invalid,
but the processor does not take an exception (the microsequencer has not yet requested
the data). In the case of an instruction cache burst, the data from the aborted cycle is
completely ignored. Pending instruction prefetches are still pending and are subsequently
run by the processor. If the second cycle is for a portion of a misaligned data operand fetch
and a bus error occurs, the processor terminates the burst operation and negates CBREQ.
Once the burst terminates, the microsequencer requests a read cycle for the second portion.
Since the burst terminated abnormally for the second cycle of the burst, the data cache
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