Motorola MC68030 User Manual page 167

Bus Operation
15 WORD OPERAND (REGISTER)
OP2
DATA BUS
D31
WORD MEMORY
MSB
XXX
OP3
Figure 7-14. Example of Misaligned Cachable Word Transfer from Word Bus
15
OP0
D31
MSB
XXX
OP1
Figure 7-15. Misaligned Long-Word Transfer to Long-Word Port
Table 7-6 shows that the processor always prefetches instructions by reading a long word
from a long-word address (A1:A0=00), regardless of port size or alignment. When the
required instruction begins at an odd-word boundary, the processor attempts to fetch the
entire 32 bits and loads both words into the instruction cache, if possible, although the
second one is the required word. Even if the instruction access is not cached, the entire 32
bits are latched into an internal cache holding register from which the two instructions words
can subsequently be referenced. Refer to Section 11 Instruction Execution Timing for a
complete description of the cache holding register and pipeline operation.
7-20
0 31
OP3 PR
D16
MC68EC030
LSB SIZ1 SIZ0
OP2
1 0
XXX
0 1
LONG WORD OPERAND
OP1 OP2
DATA BUS
LONG WORD MEMORY
LMB
UMB
XXX XXX
OP2 OP3
MC68030 USER'S MANUAL
CACHE ENTRY
OP2
MEMORY CONTROL
A2 A1 A0 DSACK1 DSACK0
0 0 1 L
L
0 1 0
0
OP3
D0
MC68EC030
LSB
SIZ1 SIZ0
OP0
0 0
XXX
1 1
OP3 N
H
H
MEMORY CONTROL
A2 A1 A0 DSACK1 DSACK0
0 1 1 L
L
1 0 0
MOTOROLA
0
L
L