Synchronous Read Cycle - Motorola MC68030 User Manual

Bus Operation
State 11
The processor negates AS and DS during S11. It holds the address and data valid during
S11 to provide address hold time for memory systems. R/W and FC0–FC2 also remain
valid throughout S11.
If more than one write cycle is required, S6-S11 are repeated for each write cycle.
The external device keeps DSACKx asserted until it detects the negation of AS or DS
(whichever it detects first). The device must remove its data and negate DSACKx within
approximately one clock period after sensing the negation of AS or DS.

7.3.4 Synchronous Read Cycle

A synchronous read cycle is terminated differently from an asynchronous read cycle;
otherwise, the cycles assert and respond to the same signals, in the same sequence.
STERM rather than DSACKx is asserted by the addressed external device to terminate a
synchronous read cycle. Since STERM must meet the synchronous setup and hold times
with respect to all rising edges of the clock while AS is asserted, it does not need to be
synchronized by the processor. Only devices with 32-bit ports may assert STERM. STERM
is also used with the CBREQ and CBACK signals during burst mode operation. It provides
a two-clock (minimum) bus cycle for 32-bit ports and single-clock (minimum) burst accesses,
although wait states can be inserted for these cycles as well. Therefore, a synchronous
cycle terminated with STERM with one wait cycle is a three-clock bus cycle. However, note
that STERM is asserted one-half clock later than DSACKx would be for a similar
asynchronous cycle with zero wait cycles (also three clocks). Thus, if dynamic bus sizing is
not needed, STERM can be used to provide more decision time in an external cache design
than is available with DSACKx for three-clock accesses.
Figure 7-31 is a flowchart of a synchronous long-word read cycle. Byte and word operations
are similar. Figure 7-32 is a functional timing diagram of a synchronous long-word read
cycle.
7-50 MC68030 USER'S MANUAL MOTOROLA