Address Bus; Address Strobe - Motorola MC68030 User Manual

Bus Operation
for user definition and two are reserved by Motorola for future use. The function code signals
are valid while AS is asserted.
At the beginning of a bus cycle, the size signals (SIZ0 and SIZ1) are driven along with ECS
and the FC0–FC2. SIZ0 and SIZ1 indicate the number of bytes remaining to be transferred
during an operand cycle (consisting of one or more bus cycles) or during a cache fill
operation from a device with a port size that is less than 32 bits. Table 7-2 shows the
encoding of SIZ0 and SIZ1. These signals are valid while AS is asserted.
The read/write (R/W) signal determines the direction of the transfer during a bus cycle. This
signal changes state, when required, at the beginning of a bus cycle and is valid while AS
is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice
versa. The signal may remain low for two consecutive write cycles.
The read-modify-write cycle signal (RMC) is asserted at the beginning of the first bus cycle
of a read-modify-write operation and remains asserted until completion of the final bus cycle
of the operation. The RMC signal is guaranteed to be negated before the end of state 0 for
a bus cycle following a read-modify-write operation.

7.1.2 Address Bus

The address bus signals (A0–A31) define the address of the byte (or the most significant
byte) to be transferred during a bus cycle. The processor places the address on the bus at
the beginning of a bus cycle. The address is valid while AS is asserted.

7.1.3 Address Strobe

AS is a timing signal that indicates the validity of an address on the address bus and of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
7-4 MC68030 USER'S MANUAL MOTOROLA